First off, thanks for the detailed and thorough description of what you've done and what the problem is.
I don't see anything fundamentally wrong with what you're doing, but since it is unusual, it's not too surprising you may be running into some issues. The assignment to cpu.dcache isn't setting a param, it's attaching a child to the cpu object (see http://m5sim.org/wiki/index.php/Simulation_Scripts_Explained#The_configuration_hierarchy). So not having that assignment is fine since you don't have a dcache. The suspicious line is this one: > 16000: system.toL2bus: The bus is now occupied from tick 16000 to 4831955816 Somehow in the code in src/mem/bus.cc that decides how long a packet is going to occupy the bus, something is going very wrong. I suggest stepping through this in gdb (use --debug-break to stop at cycle 16000, then set a breakpoint in Bus::calcPacketTiming()). Steve _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
