changeset 05b1a077977b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=05b1a077977b
description:
ARM: Make the TLB a little bit faster by moving most recently used
items to front of list
diffstat:
src/arch/arm/tlb.cc | 35 +++++++++++++++++++++--------------
src/arch/arm/tlb.hh | 3 +--
2 files changed, 22 insertions(+), 16 deletions(-)
diffs (107 lines):
diff -r 1e789578729e -r 05b1a077977b src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc Fri Oct 01 16:04:02 2010 -0500
+++ b/src/arch/arm/tlb.cc Fri Oct 01 16:04:04 2010 -0500
@@ -65,10 +65,11 @@
using namespace ArmISA;
TLB::TLB(const Params *p)
- : BaseTLB(p), size(p->size), nlu(0)
+ : BaseTLB(p), size(p->size)
#if FULL_SYSTEM
, tableWalker(p->walker)
#endif
+ , rangeMRU(1)
{
table = new TlbEntry[size];
memset(table, 0, sizeof(TlbEntry[size]));
@@ -98,19 +99,25 @@
TlbEntry*
TLB::lookup(Addr va, uint8_t cid, bool functional)
{
- // XXX This should either turn into a TlbMap or add caching
TlbEntry *retval = NULL;
- // Do some kind of caching, fast indexing, anything
+ // Maitaining LRU array
int x = 0;
while (retval == NULL && x < size) {
if (table[x].match(va, cid)) {
- retval = &table[x];
- if (x == nlu && !functional)
- nextnlu();
+ // We only move the hit entry ahead when the position is higher
than rangeMRU
+ if (x > rangeMRU) {
+ TlbEntry tmp_entry = table[x];
+ for(int i = x; i > 0; i--)
+ table[i] = table[i-1];
+ table[0] = tmp_entry;
+ retval = &table[0];
+ } else {
+ retval = &table[x];
+ }
break;
}
x++;
@@ -134,16 +141,17 @@
entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp,
entry.xn, entry.ap, entry.domain);
- if (table[nlu].valid)
+ if (table[size-1].valid)
DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x
ap:%d\n",
- table[nlu].vpn << table[nlu].N, table[nlu].asid, table[nlu].pfn <<
table[nlu].N,
- table[nlu].size, table[nlu].ap);
+ table[size-1].vpn << table[size-1].N, table[size-1].asid,
+ table[size-1].pfn << table[size-1].N, table[size-1].size,
+ table[size-1].ap);
- // XXX Update caching, lookup table etc
- table[nlu] = entry;
+ //inserting to MRU position and evicting the LRU one
- // XXX Figure out how entries are generally inserted in ARM
- nextnlu();
+ for(int i = size-1; i > 0; i--)
+ table[i] = table[i-1];
+ table[0] = entry;
}
void
@@ -177,7 +185,6 @@
}
memset(table, 0, sizeof(TlbEntry[size]));
- nlu = 0;
}
diff -r 1e789578729e -r 05b1a077977b src/arch/arm/tlb.hh
--- a/src/arch/arm/tlb.hh Fri Oct 01 16:04:02 2010 -0500
+++ b/src/arch/arm/tlb.hh Fri Oct 01 16:04:04 2010 -0500
@@ -88,7 +88,6 @@
TlbEntry *table; // the Page Table
int size; // TLB Size
- int nlu; // not last used entry (for replacement)
uint32_t _attr; // Memory attributes for last accessed TLB entry
@@ -96,7 +95,6 @@
TableWalker *tableWalker;
#endif
- void nextnlu() { if (++nlu >= size) nlu = 0; }
/** Lookup an entry in the TLB
* @param vpn virtual address
* @param asn context id/address space id to use
@@ -118,6 +116,7 @@
Stats::Formula misses;
Stats::Formula accesses;
+ int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
public:
typedef ArmTLBParams Params;
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
