This has come up in ARM and also in X86 with its STUPD (store with update) microop. The problem has been updating the base register when, one, the instruction may fault after initiateAcc and the initial value is lost, and two, completeAcc isn't called by O3. The problem is compounded by the fact that O3 can speculatively update the register and recover the old value if there's a fault, and the simple CPUs can't.
What if we changed the instructions that update the base to update the base in initiateAcc and store the old value in an architecturally invisible register? Then, if the instruction faults for whatever reason, the fault object can know it needs to restore the old value of the base before vectoring into the fault handler. If the instruction completes normally the value of the base will be updated for consumption by later instructions, and the value of the backup register can be ignored. I don't -think- there would be performance distortions from this since the actual number of sources/destinations doesn't matter, and this would be at least a little more realistic and simulator level performant than splitting things into microops. This would be pretty easy to implement, I think, and would be entirely contained in existing mechanisms in the ISA, so there isn't really any question there. What I'd like to know is whether people think this is a reasonable approach to this problem in the first place. Gabe _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
