On 10/23/10 18:18, Ali Saidi wrote: > On Oct 19, 2010, at 12:57 PM, Gabe Black wrote: > >> Gabe Black wrote: >>> nathan binkert wrote: >>> >>>>> Whether there's an interrupt available is already tracked by ISA >>>>> dependent code by the Interrupts object which lives at commit. Why does >>>>> fetch need to know? Anything it fetches is just going to get blown away >>>>> anyway. >>>>> >>>>> >>>> The point is, you want to redirect fetch intelligently. When there is >>>> an interrupt, you just want to insert it into the instruction stream >>>> (like an asynchronous branch), not treat it like an exception. If you >>>> treat it like an exception, as you say, you blow a lot of useful work >>>> away. There's no reason to do this with an interrupt. Interrupts are >>>> already expensive operations. It would not be good to unreasonably >>>> make them more expensive (especially if real machines don't). >>>> >>>> Nate >>>> _______________________________________________ >>>> m5-dev mailing list >>>> [email protected] >>>> http://m5sim.org/mailman/listinfo/m5-dev >>>> >>>> >>> Well, that's how it works today anyway. If you write to the TC I'm >>> pretty sure you flush the pipe, and you need to flush the pipe to vector >>> to an interrupt. >> That should read "and you need to write to the TC to vector to an >> interrupt". > Yes, but interrupts don't actually write to the TC. > > Ali > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev
They don't? The interrupts object returns an InterruptFault, that inherits from AlphaFault and uses its invoke method, and that sets IPR_EXC_ADDR and the pc with the pc. Or are we talking about different things? Gabe _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
