changeset a1a85250e897 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a1a85250e897
description:
ARM: Add full-system regressions
diffstat:
tests/SConscript
| 21 +-
tests/configs/realview-simple-atomic.py
| 96 +
tests/configs/realview-simple-timing.py
| 98 +
tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
| 8 +-
tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
| 32 +-
tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
| 4 +-
tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
| 8 +-
tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
| 32 +-
tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
| 6 +-
tests/long/10.mcf/ref/arm/linux/simple-timing/simout
| 10 +-
tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
| 32 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
| 578 ++++++++++
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
| 39 +
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
| 16 +
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
| 399 ++++++
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
| 1 +
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
| 0
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
| 575 +++++++++
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
| 39 +
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
| 16 +
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
| 483 ++++++++
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status
| 1 +
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
| 0
util/regress
| 2 +-
25 files changed, 2464 insertions(+), 34 deletions(-)
diffs (truncated from 2739 to 300 lines):
diff -r 85a8198aa2ff -r a1a85250e897 tests/SConscript
--- a/tests/SConscript Mon Nov 08 13:58:25 2010 -0600
+++ b/tests/SConscript Mon Nov 08 13:58:25 2010 -0600
@@ -30,7 +30,7 @@
# Kevin Lim
import os, signal
-import sys
+import sys, time
import glob
from SCons.Script.SConscript import SConsEnvironment
@@ -102,11 +102,26 @@
if env['BATCH']:
cmd = '%s -t %d %s' % (env['BATCH_CMD'], timeout, cmd)
+ pre_exec_time = time.time()
status = env.Execute(env.subst(cmd, target=target, source=source))
if status == 0:
# M5 terminated normally.
# Run diff on output & ref directories to find differences.
# Exclude the stats file since we will use diff-out on that.
+
+ # NFS file systems can be annoying and not have updated yet
+ # wait until we see the file modified
+ statsdiff = os.path.join(tgt_dir, 'statsdiff')
+ m_time = 0
+ nap = 0
+ while m_time < pre_exec_time and nap < 10:
+ try:
+ m_time = os.stat(statsdiff).st_mtime
+ except OSError:
+ pass
+ time.sleep(1)
+ nap += 1
+
outdiff = os.path.join(tgt_dir, 'outdiff')
diffcmd = 'diff -ubrs %s ${SOURCES[2].dir} %s > %s' \
% (output_ignore_args, tgt_dir, outdiff)
@@ -114,7 +129,6 @@
print "===== Output differences ====="
print contents(outdiff)
# Run diff-out on stats.txt file
- statsdiff = os.path.join(tgt_dir, 'statsdiff')
diffcmd = '$DIFFOUT ${SOURCES[2]} %s > %s' \
% (os.path.join(tgt_dir, 'stats.txt'), statsdiff)
diffcmd = env.subst(diffcmd, target=target, source=source)
@@ -260,6 +274,9 @@
if env['TARGET_ISA'] == 'sparc':
configs += ['t1000-simple-atomic',
't1000-simple-timing']
+ if env['TARGET_ISA'] == 'arm':
+ configs += ['realview-simple-atomic',
+ 'realview-simple-timing']
else:
configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest',
diff -r 85a8198aa2ff -r a1a85250e897 tests/configs/realview-simple-atomic.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/configs/realview-simple-atomic.py Mon Nov 08 13:58:25 2010 -0600
@@ -0,0 +1,96 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+ latency = '1ns'
+ block_size = 64
+ mshrs = 4
+ tgts_per_mshr = 8
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+ block_size = 64
+ latency = '10ns'
+ mshrs = 92
+ tgts_per_mshr = 16
+ write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+ assoc = 8
+ block_size = 64
+ latency = '50ns'
+ mshrs = 20
+ size = '1kB'
+ tgts_per_mshr = 12
+ addr_range=AddrRange(0, size='128MB')
+ forward_snoops = False
+
+#cpu
+cpu = AtomicSimpleCPU(cpu_id=0)
+#the system
+system = FSConfig.makeLinuxArmSystem('atomic', None, False, "RealView_PBX")
+system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+system.bridge.filter_ranges_b=[AddrRange(0, size='128MB')]
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.port
+system.iocache.mem_side = system.membus.port
+
+system.cpu = cpu
+#create the l1/l2 bus
+system.toL2Bus = Bus()
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.mem_side = system.membus.port
+
+#connect up the cpu and l1s
+cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4))
+# connect cpu level-1 caches to shared level-2 cache
+cpu.connectMemPorts(system.toL2Bus)
+cpu.clock = '2GHz'
+
+root = Root(system=system)
+m5.ticks.setGlobalFrequency('1THz')
+
diff -r 85a8198aa2ff -r a1a85250e897 tests/configs/realview-simple-timing.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/configs/realview-simple-timing.py Mon Nov 08 13:58:25 2010 -0600
@@ -0,0 +1,98 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+ latency = '1ns'
+ block_size = 64
+ mshrs = 4
+ tgts_per_mshr = 8
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+ block_size = 64
+ latency = '10ns'
+ mshrs = 92
+ tgts_per_mshr = 16
+ write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+ assoc = 8
+ block_size = 64
+ latency = '50ns'
+ mshrs = 20
+ size = '1kB'
+ tgts_per_mshr = 12
+ addr_range=AddrRange(0, size='128MB')
+ forward_snoops = False
+
+#cpu
+cpu = TimingSimpleCPU(cpu_id=0)
+#the system
+system = FSConfig.makeLinuxArmSystem('timing', None, False, "RealView_PBX")
+
+system.cpu = cpu
+#create the l1/l2 bus
+system.toL2Bus = Bus()
+system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+system.bridge.filter_ranges_b=[AddrRange(0, size='128MB')]
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.port
+system.iocache.mem_side = system.membus.port
+
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.mem_side = system.membus.port
+
+#connect up the cpu and l1s
+cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4))
+# connect cpu level-1 caches to shared level-2 cache
+cpu.connectMemPorts(system.toL2Bus)
+cpu.clock = '2GHz'
+
+root = Root(system=system)
+m5.ticks.setGlobalFrequency('1THz')
+
diff -r 85a8198aa2ff -r a1a85250e897
tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini Mon Nov 08
13:58:25 2010 -0600
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini Mon Nov 08
13:58:25 2010 -0600
@@ -57,7 +57,7 @@
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
diff -r 85a8198aa2ff -r a1a85250e897
tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout Mon Nov 08
13:58:25 2010 -0600
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout Mon Nov 08
13:58:25 2010 -0600
@@ -5,10 +5,10 @@
All Rights Reserved
-M5 compiled Aug 24 2010 15:34:40
-M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
-M5 started Aug 24 2010 15:35:18
-M5 executing on zizzer
+M5 compiled Oct 5 2010 14:46:04
+M5 revision 878ec5a6f4d1+ 7707+ default qtip tip ext/fs_regressions.patch
+M5 started Oct 5 2010 15:01:57
+M5 executing on aus-bc2-b14
command line: build/ARM_SE/m5.fast -d
build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py
build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff -r 85a8198aa2ff -r a1a85250e897
tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt Mon Nov 08
13:58:25 2010 -0600
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt Mon Nov 08
13:58:25 2010 -0600
@@ -1,16 +1,28 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 4210115 #
Simulator instruction rate (inst/s)
-host_mem_usage 202336 #
Number of bytes of host memory used
-host_seconds 142.65 #
Real time elapsed on the host
-host_tick_rate 2105134486 #
Simulator tick rate (ticks/s)
+host_inst_rate 4265359 #
Simulator instruction rate (inst/s)
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