changeset f61e079ad05e in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=f61e079ad05e description: ARM: Update SE stats for TLB stats additions
diffstat: tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini | 2 +- tests/long/00.gzip/ref/arm/linux/simple-atomic/simout | 10 +- tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt | 8 +- tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini | 2 +- tests/long/00.gzip/ref/arm/linux/simple-timing/simout | 8 +- tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt | 32 ++++++++++- tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini | 2 +- tests/long/10.mcf/ref/arm/linux/simple-atomic/simout | 10 +- tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt | 8 +- tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini | 2 +- tests/long/10.mcf/ref/arm/linux/simple-timing/simout | 10 +- tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt | 8 +- tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini | 6 +- tests/long/20.parser/ref/arm/linux/simple-atomic/simout | 10 +- tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt | 32 ++++++++++- tests/long/20.parser/ref/arm/linux/simple-timing/config.ini | 4 +- tests/long/20.parser/ref/arm/linux/simple-timing/simout | 8 +- tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt | 32 ++++++++++- tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini | 4 +- tests/long/30.eon/ref/arm/linux/simple-atomic/simout | 10 +- tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt | 32 ++++++++++- tests/long/30.eon/ref/arm/linux/simple-timing/config.ini | 2 +- tests/long/30.eon/ref/arm/linux/simple-timing/simout | 8 +- tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt | 32 ++++++++++- tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini | 4 +- tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout | 10 +- tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt | 32 ++++++++++- tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini | 2 +- tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout | 8 +- tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt | 32 ++++++++++- tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini | 4 +- tests/long/50.vortex/ref/arm/linux/simple-atomic/simout | 10 +- tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt | 32 ++++++++++- tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini | 2 +- tests/long/50.vortex/ref/arm/linux/simple-timing/simout | 8 +- tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt | 32 ++++++++++- tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini | 4 +- tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout | 10 +- tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt | 32 ++++++++++- tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini | 2 +- tests/long/60.bzip2/ref/arm/linux/simple-timing/simout | 8 +- tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt | 32 ++++++++++- tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini | 4 +- tests/long/70.twolf/ref/arm/linux/simple-atomic/simout | 14 ++-- tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt | 32 ++++++++++- tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini | 2 +- tests/long/70.twolf/ref/arm/linux/simple-timing/simout | 10 ++- tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt | 32 ++++++++++- tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini | 2 +- tests/quick/00.hello/ref/arm/linux/simple-atomic/simout | 10 +- tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt | 32 ++++++++++- 51 files changed, 511 insertions(+), 173 deletions(-) diffs (truncated from 1442 to 300 lines): diff -r a1a85250e897 -r f61e079ad05e tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini --- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini Mon Nov 08 13:58:25 2010 -0600 +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini Mon Nov 08 13:59:35 2010 -0600 @@ -52,7 +52,7 @@ [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic egid=100 env= errout=cerr diff -r a1a85250e897 -r f61e079ad05e tests/long/00.gzip/ref/arm/linux/simple-atomic/simout --- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout Mon Nov 08 13:58:25 2010 -0600 +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout Mon Nov 08 13:59:35 2010 -0600 @@ -5,11 +5,11 @@ All Rights Reserved -M5 compiled Oct 5 2010 14:46:04 -M5 revision 878ec5a6f4d1+ 7707+ default qtip tip ext/fs_regressions.patch -M5 started Oct 5 2010 15:01:57 -M5 executing on aus-bc2-b14 -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic +M5 compiled Oct 11 2010 18:37:23 +M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip +M5 started Oct 11 2010 19:16:15 +M5 executing on aus-bc3-b4 +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff -r a1a85250e897 -r f61e079ad05e tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt --- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt Mon Nov 08 13:58:25 2010 -0600 +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt Mon Nov 08 13:59:35 2010 -0600 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4265359 # Simulator instruction rate (inst/s) -host_mem_usage 252884 # Number of bytes of host memory used -host_seconds 140.80 # Real time elapsed on the host -host_tick_rate 2132757259 # Simulator tick rate (ticks/s) +host_inst_rate 2821771 # Simulator instruction rate (inst/s) +host_mem_usage 253968 # Number of bytes of host memory used +host_seconds 212.84 # Real time elapsed on the host +host_tick_rate 1410937507 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 600581394 # Number of instructions simulated sim_seconds 0.300302 # Number of seconds simulated diff -r a1a85250e897 -r f61e079ad05e tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini Mon Nov 08 13:58:25 2010 -0600 +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini Mon Nov 08 13:59:35 2010 -0600 @@ -157,7 +157,7 @@ env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/gzip +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff -r a1a85250e897 -r f61e079ad05e tests/long/00.gzip/ref/arm/linux/simple-timing/simout --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout Mon Nov 08 13:58:25 2010 -0600 +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout Mon Nov 08 13:59:35 2010 -0600 @@ -5,10 +5,10 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:50 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 15:05:18 -M5 executing on phenom +M5 compiled Oct 11 2010 18:37:23 +M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip +M5 started Oct 11 2010 18:44:50 +M5 executing on aus-bc3-b4 command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff -r a1a85250e897 -r f61e079ad05e tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt Mon Nov 08 13:58:25 2010 -0600 +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt Mon Nov 08 13:59:35 2010 -0600 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1338185 # Simulator instruction rate (inst/s) -host_mem_usage 196956 # Number of bytes of host memory used -host_seconds 447.34 # Real time elapsed on the host -host_tick_rate 1781116972 # Simulator tick rate (ticks/s) +host_inst_rate 652561 # Simulator instruction rate (inst/s) +host_mem_usage 261720 # Number of bytes of host memory used +host_seconds 917.34 # Real time elapsed on the host +host_tick_rate 868554806 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 598619824 # Number of instructions simulated sim_seconds 0.796760 # Number of seconds simulated @@ -74,8 +74,20 @@ system.cpu.dcache.warmup_cycle 537003000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 392389 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -139,8 +151,20 @@ system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses diff -r a1a85250e897 -r f61e079ad05e tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini Mon Nov 08 13:58:25 2010 -0600 +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini Mon Nov 08 13:59:35 2010 -0600 @@ -52,7 +52,7 @@ [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic egid=100 env= errout=cerr diff -r a1a85250e897 -r f61e079ad05e tests/long/10.mcf/ref/arm/linux/simple-atomic/simout --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout Mon Nov 08 13:58:25 2010 -0600 +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout Mon Nov 08 13:59:35 2010 -0600 @@ -5,11 +5,11 @@ All Rights Reserved -M5 compiled Oct 5 2010 14:46:04 -M5 revision 878ec5a6f4d1+ 7707+ default qtip tip ext/fs_regressions.patch -M5 started Oct 5 2010 15:01:57 -M5 executing on aus-bc2-b14 -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic +M5 compiled Oct 11 2010 18:37:23 +M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip +M5 started Oct 11 2010 18:40:32 +M5 executing on aus-bc3-b4 +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff -r a1a85250e897 -r f61e079ad05e tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt Mon Nov 08 13:58:25 2010 -0600 +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt Mon Nov 08 13:59:35 2010 -0600 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3851747 # Simulator instruction rate (inst/s) -host_mem_usage 385600 # Number of bytes of host memory used -host_seconds 23.68 # Real time elapsed on the host -host_tick_rate 2289652632 # Simulator tick rate (ticks/s) +host_inst_rate 2560594 # Simulator instruction rate (inst/s) +host_mem_usage 386656 # Number of bytes of host memory used +host_seconds 35.62 # Real time elapsed on the host +host_tick_rate 1522136495 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91202735 # Number of instructions simulated sim_seconds 0.054216 # Number of seconds simulated diff -r a1a85250e897 -r f61e079ad05e tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini Mon Nov 08 13:58:25 2010 -0600 +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini Mon Nov 08 13:59:35 2010 -0600 @@ -152,7 +152,7 @@ [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing +cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing egid=100 env= errout=cerr diff -r a1a85250e897 -r f61e079ad05e tests/long/10.mcf/ref/arm/linux/simple-timing/simout --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout Mon Nov 08 13:58:25 2010 -0600 +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout Mon Nov 08 13:59:35 2010 -0600 @@ -5,11 +5,11 @@ All Rights Reserved -M5 compiled Oct 5 2010 14:46:04 -M5 revision 878ec5a6f4d1+ 7707+ default qtip tip ext/fs_regressions.patch -M5 started Oct 5 2010 15:02:21 -M5 executing on aus-bc2-b14 -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing +M5 compiled Oct 11 2010 18:37:23 +M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip +M5 started Oct 11 2010 18:41:18 +M5 executing on aus-bc3-b4 +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff -r a1a85250e897 -r f61e079ad05e tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt Mon Nov 08 13:58:25 2010 -0600 +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt Mon Nov 08 13:59:35 2010 -0600 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 795252 # Simulator instruction rate (inst/s) -host_mem_usage 393312 # Number of bytes of host memory used -host_seconds 114.65 # Real time elapsed on the host -host_tick_rate 1291628028 # Simulator tick rate (ticks/s) +host_inst_rate 587679 # Simulator instruction rate (inst/s) +host_mem_usage 394372 # Number of bytes of host memory used +host_seconds 155.15 # Real time elapsed on the host +host_tick_rate 954493550 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91176087 # Number of instructions simulated sim_seconds 0.148086 # Number of seconds simulated diff -r a1a85250e897 -r f61e079ad05e tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini --- a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini Mon Nov 08 13:58:25 2010 -0600 +++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini Mon Nov 08 13:59:35 2010 -0600 @@ -52,14 +52,14 @@ [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff -r a1a85250e897 -r f61e079ad05e tests/long/20.parser/ref/arm/linux/simple-atomic/simout --- a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout Mon Nov 08 13:58:25 2010 -0600 +++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/simout Mon Nov 08 13:59:35 2010 -0600 @@ -5,11 +5,11 @@ All Rights Reserved -M5 compiled Aug 24 2010 15:34:40 -M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase -M5 started Aug 24 2010 15:44:22 -M5 executing on zizzer -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic +M5 compiled Oct 11 2010 18:37:23 +M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip +M5 started Oct 11 2010 18:37:50 +M5 executing on aus-bc3-b4 +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff -r a1a85250e897 -r f61e079ad05e tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt --- a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt Mon Nov 08 13:58:25 2010 -0600 +++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt Mon Nov 08 13:59:35 2010 -0600 @@ -1,16 +1,28 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4358961 # Simulator instruction rate (inst/s) -host_mem_usage 206092 # Number of bytes of host memory used -host_seconds 128.79 # Real time elapsed on the host -host_tick_rate 2218414400 # Simulator tick rate (ticks/s) +host_inst_rate 2845430 # Simulator instruction rate (inst/s) +host_mem_usage 257528 # Number of bytes of host memory used +host_seconds 197.30 # Real time elapsed on the host +host_tick_rate 1448130657 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 561403855 # Number of instructions simulated sim_seconds 0.285717 # Number of seconds simulated sim_ticks 285716811500 # Number of ticks simulated system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
