changeset 5ba6ed672cda in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5ba6ed672cda
description:
Update EIO regressions for last set of patches
diffstat:
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini | 2 +-
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr | 18 +-
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout | 15 +-
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt | 50 +
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr | 18 +-
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout | 15 +-
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt | 233 ++
tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr | 24 +-
tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout | 21 +-
tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt | 712 ++++++++
tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr | 24 +-
tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout | 21 +-
tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt | 812
++++++++++
13 files changed, 1904 insertions(+), 61 deletions(-)
diffs (truncated from 2055 to 300 lines):
diff -r f97a5f4d0879 -r 5ba6ed672cda
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini Tue Nov
09 11:03:40 2010 -0800
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini Wed Nov
10 00:45:50 2010 -0600
@@ -53,7 +53,7 @@
type=EioProcess
chkpt=
errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
diff -r f97a5f4d0879 -r 5ba6ed672cda
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr Tue Nov
09 11:03:40 2010 -0800
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr Wed Nov
10 00:45:50 2010 -0600
@@ -1,9 +1,9 @@
-Traceback (most recent call last):
- File "<string>", line 1, in <module>
- File "/arm/scratch/alisai01/m5/src/python/m5/main.py", line 359, in main
- exec filecode in scope
- File "tests/run.py", line 78, in <module>
- execfile(joinpath(tests_root, category, name, 'test.py'))
- File "tests/quick/20.eio-short/test.py", line 29, in <module>
- root.system.cpu.workload = EioProcess(file = binpath('anagram',
-NameError: name 'EioProcess' is not defined
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+hack: be nice to actually delete the event here
+
+gzip: stdout: Broken pipe
diff -r f97a5f4d0879 -r 5ba6ed672cda
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout Tue Nov
09 11:03:40 2010 -0800
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout Wed Nov
10 00:45:50 2010 -0600
@@ -1,5 +1,3 @@
-Redirecting stdout to
build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic/simout
-Redirecting stderr to
build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -7,8 +5,13 @@
All Rights Reserved
-M5 compiled Nov 2 2010 21:30:55
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov 2 2010 21:33:04
-M5 executing on aus-bc2-b15
+M5 compiled Nov 9 2010 10:38:04
+M5 revision f4362ffd810f+ 7737+ default tip
+M5 started Nov 9 2010 22:11:58
+M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re
tests/run.py
build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+main dictionary has 1245 entries
+49508 bytes wasted
+>Exiting @ tick 250015500 because a thread reached the max instruction count
diff -r f97a5f4d0879 -r 5ba6ed672cda
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt Tue Nov
09 11:03:40 2010 -0800
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt Wed Nov
10 00:45:50 2010 -0600
@@ -0,0 +1,50 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 2960881 #
Simulator instruction rate (inst/s)
+host_mem_usage 193980 #
Number of bytes of host memory used
+host_seconds 0.17 #
Real time elapsed on the host
+host_tick_rate 1478428114 #
Simulator tick rate (ticks/s)
+sim_freq 1000000000000 #
Frequency of simulated ticks
+sim_insts 500001 #
Number of instructions simulated
+sim_seconds 0.000250 #
Number of seconds simulated
+sim_ticks 250015500 #
Number of ticks simulated
+system.cpu.dtb.data_accesses 180793 #
DTB accesses
+system.cpu.dtb.data_acv 0 #
DTB access violations
+system.cpu.dtb.data_hits 180775 #
DTB hits
+system.cpu.dtb.data_misses 18 #
DTB misses
+system.cpu.dtb.fetch_accesses 0 #
ITB accesses
+system.cpu.dtb.fetch_acv 0 #
ITB acv
+system.cpu.dtb.fetch_hits 0 #
ITB hits
+system.cpu.dtb.fetch_misses 0 #
ITB misses
+system.cpu.dtb.read_accesses 124443 #
DTB read accesses
+system.cpu.dtb.read_acv 0 #
DTB read access violations
+system.cpu.dtb.read_hits 124435 #
DTB read hits
+system.cpu.dtb.read_misses 8 #
DTB read misses
+system.cpu.dtb.write_accesses 56350 #
DTB write accesses
+system.cpu.dtb.write_acv 0 #
DTB write access violations
+system.cpu.dtb.write_hits 56340 #
DTB write hits
+system.cpu.dtb.write_misses 10 #
DTB write misses
+system.cpu.idle_fraction 0 #
Percentage of idle cycles
+system.cpu.itb.data_accesses 0 #
DTB accesses
+system.cpu.itb.data_acv 0 #
DTB access violations
+system.cpu.itb.data_hits 0 #
DTB hits
+system.cpu.itb.data_misses 0 #
DTB misses
+system.cpu.itb.fetch_accesses 500032 #
ITB accesses
+system.cpu.itb.fetch_acv 0 #
ITB acv
+system.cpu.itb.fetch_hits 500019 #
ITB hits
+system.cpu.itb.fetch_misses 13 #
ITB misses
+system.cpu.itb.read_accesses 0 #
DTB read accesses
+system.cpu.itb.read_acv 0 #
DTB read access violations
+system.cpu.itb.read_hits 0 #
DTB read hits
+system.cpu.itb.read_misses 0 #
DTB read misses
+system.cpu.itb.write_accesses 0 #
DTB write accesses
+system.cpu.itb.write_acv 0 #
DTB write access violations
+system.cpu.itb.write_hits 0 #
DTB write hits
+system.cpu.itb.write_misses 0 #
DTB write misses
+system.cpu.not_idle_fraction 1 #
Percentage of non-idle cycles
+system.cpu.numCycles 500032 #
number of cpu cycles simulated
+system.cpu.num_insts 500001 #
Number of instructions executed
+system.cpu.num_refs 180793 #
Number of memory references
+system.cpu.workload.PROG:num_syscalls 18 #
Number of system calls
+
+---------- End Simulation Statistics ----------
diff -r f97a5f4d0879 -r 5ba6ed672cda
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr Tue Nov
09 11:03:40 2010 -0800
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr Wed Nov
10 00:45:50 2010 -0600
@@ -1,9 +1,9 @@
-Traceback (most recent call last):
- File "<string>", line 1, in <module>
- File "/arm/scratch/alisai01/m5/src/python/m5/main.py", line 359, in main
- exec filecode in scope
- File "tests/run.py", line 78, in <module>
- execfile(joinpath(tests_root, category, name, 'test.py'))
- File "tests/quick/20.eio-short/test.py", line 29, in <module>
- root.system.cpu.workload = EioProcess(file = binpath('anagram',
-NameError: name 'EioProcess' is not defined
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+hack: be nice to actually delete the event here
+
+gzip: stdout: Broken pipe
diff -r f97a5f4d0879 -r 5ba6ed672cda
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout Tue Nov
09 11:03:40 2010 -0800
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout Wed Nov
10 00:45:50 2010 -0600
@@ -1,5 +1,3 @@
-Redirecting stdout to
build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing/simout
-Redirecting stderr to
build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -7,8 +5,13 @@
All Rights Reserved
-M5 compiled Nov 2 2010 21:30:55
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov 2 2010 21:31:02
-M5 executing on aus-bc2-b15
+M5 compiled Nov 9 2010 10:38:04
+M5 revision f4362ffd810f+ 7737+ default tip
+M5 started Nov 9 2010 22:11:58
+M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re
tests/run.py
build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+main dictionary has 1245 entries
+49508 bytes wasted
+>Exiting @ tick 727929000 because a thread reached the max instruction count
diff -r f97a5f4d0879 -r 5ba6ed672cda
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt Tue Nov
09 11:03:40 2010 -0800
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt Wed Nov
10 00:45:50 2010 -0600
@@ -0,0 +1,233 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1193890 #
Simulator instruction rate (inst/s)
+host_mem_usage 201748 #
Number of bytes of host memory used
+host_seconds 0.42 #
Real time elapsed on the host
+host_tick_rate 1737027103 #
Simulator tick rate (ticks/s)
+sim_freq 1000000000000 #
Frequency of simulated ticks
+sim_insts 500001 #
Number of instructions simulated
+sim_seconds 0.000728 #
Number of seconds simulated
+sim_ticks 727929000 #
Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 124435 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 56000
# average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000
# average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 124120 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 17640000 #
number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.002531 #
miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 315 #
number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 16695000
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 #
mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 315 #
number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 56340 #
number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56000
# average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000
# average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 56201 #
number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 7784000 #
number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.002467 #
miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 139 #
number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 7367000
# number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 #
mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 139 #
number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 397.182819 #
Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 0 #
number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 #
number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0
# number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 #
number of cache copies performed
+system.cpu.dcache.demand_accesses 180775 #
number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 56000 #
average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53000
# average overall mshr miss latency
+system.cpu.dcache.demand_hits 180321 #
number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 25424000 #
number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.002511 #
miss rate for demand accesses
+system.cpu.dcache.demand_misses 454 #
number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 #
number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 24062000
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.002511 #
mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 454 #
number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 #
number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.070111 #
Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 287.175167 #
Average occupied blocks per context
+system.cpu.dcache.overall_accesses 180775 #
number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 56000
# average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53000
# average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 180321 #
number of overall hits
+system.cpu.dcache.overall_miss_latency 25424000 #
number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.002511 #
miss rate for overall accesses
+system.cpu.dcache.overall_misses 454 #
number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 #
number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 24062000
# number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.002511 #
mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 454 #
number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
+system.cpu.dcache.replacements 0 #
number of replacements
+system.cpu.dcache.sampled_refs 454 #
Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 287.175167 #
Cycle average of tags in use
+system.cpu.dcache.total_refs 180321 #
Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 #
number of writebacks
+system.cpu.dtb.data_accesses 180793 #
DTB accesses
+system.cpu.dtb.data_acv 0 #
DTB access violations
+system.cpu.dtb.data_hits 180775 #
DTB hits
+system.cpu.dtb.data_misses 18 #
DTB misses
+system.cpu.dtb.fetch_accesses 0 #
ITB accesses
+system.cpu.dtb.fetch_acv 0 #
ITB acv
+system.cpu.dtb.fetch_hits 0 #
ITB hits
+system.cpu.dtb.fetch_misses 0 #
ITB misses
+system.cpu.dtb.read_accesses 124443 #
DTB read accesses
+system.cpu.dtb.read_acv 0 #
DTB read access violations
+system.cpu.dtb.read_hits 124435 #
DTB read hits
+system.cpu.dtb.read_misses 8 #
DTB read misses
+system.cpu.dtb.write_accesses 56350 #
DTB write accesses
+system.cpu.dtb.write_acv 0 #
DTB write access violations
+system.cpu.dtb.write_hits 56340 #
DTB write hits
+system.cpu.dtb.write_misses 10 #
DTB write misses
+system.cpu.icache.ReadReq_accesses 500020 #
number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 56000
# average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000
# average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 499617 #
number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 22568000 #
number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000806 #
miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 403 #
number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 21359000
# number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 #
mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 403 #
number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
+system.cpu.icache.avg_refs 1239.744417 #
Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs 0 #
number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 #
number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0
# number of cycles access was blocked
+system.cpu.icache.cache_copies 0 #
number of cache copies performed
+system.cpu.icache.demand_accesses 500020 #
number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 56000 #
average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 53000
# average overall mshr miss latency
+system.cpu.icache.demand_hits 499617 #
number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 22568000 #
number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000806 #
miss rate for demand accesses
+system.cpu.icache.demand_misses 403 #
number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 #
number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 21359000
# number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000806 #
mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 403 #
number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 #
number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 #
number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 #
Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.129371 #
Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 264.952126 #
Average occupied blocks per context
+system.cpu.icache.overall_accesses 500020 #
number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 56000
# average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 53000
# average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 499617 #
number of overall hits
+system.cpu.icache.overall_miss_latency 22568000 #
number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000806 #
miss rate for overall accesses
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