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If you knew the two parts coming back were halves of an unaligned access, it might be reasonable to try and combine them rather than forcing the second half to retry, but this seems OK to me. src/cpu/simple/timing.cc <http://reviews.m5sim.org/r/304/#comment697> need braces here around the if clause - Steve On 2010-11-11 16:13:08, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/304/ > ----------------------------------------------------------- > > (Updated 2010-11-11 16:13:08) > > > Review request for Default. > > > Summary > ------- > > CPU: Fix bug when a split transaction is issued to a faster cache > > In the case of a split transaction and a cache that is faster than a CPU we > could get two responses before next_tick expires. Add an event that is > scheduled in this case and return false rather than asserting. > > > Diffs > ----- > > src/cpu/simple/timing.hh 3155a9ccb66b > src/cpu/simple/timing.cc 3155a9ccb66b > > Diff: http://reviews.m5sim.org/r/304/diff > > > Testing > ------- > > > Thanks, > > Ali > >
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