changeset 79adfecb2b8a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=79adfecb2b8a
description:
ARM: Fix SRS instruction to micro-code memory operation and register
update.
Previously the SRS instruction attempted to writeback in initiateAcc()
which
worked until a recent change, but was incorrect.
diffstat:
src/arch/arm/isa/insts/str.isa | 11 ++++++++---
1 files changed, 8 insertions(+), 3 deletions(-)
diffs (32 lines):
diff -r 434b5dfb87d9 -r 79adfecb2b8a src/arch/arm/isa/insts/str.isa
--- a/src/arch/arm/isa/insts/str.isa Mon Nov 15 14:04:03 2010 -0600
+++ b/src/arch/arm/isa/insts/str.isa Mon Nov 15 14:04:03 2010 -0600
@@ -112,8 +112,6 @@
Mem.ud = (uint64_t)cSwap(LR.uw, cpsr.e) |
((uint64_t)cSwap(Spsr.uw, cpsr.e) << 32);
'''
- if self.writeback:
- accCode += "SpMode = SpMode + %s;\n" % wbDiff
global header_output, decoder_output, exec_output
@@ -122,11 +120,18 @@
"postacc_code": "" }
codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
+ wbDecl = None
+ if self.writeback:
+ wbDecl = '''MicroAddiUop(machInst,
+ intRegInMode((OperatingMode)regMode, INTREG_SP),
+ intRegInMode((OperatingMode)regMode, INTREG_SP),
+ %d);''' % wbDiff
+
(newHeader,
newDecoder,
newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
["ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], [],
- base = 'SrsOp')
+ 'SrsOp', wbDecl)
header_output += newHeader
decoder_output += newDecoder
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