changeset 434b5dfb87d9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=434b5dfb87d9
description:
CPU: Fix bug when a split transaction is issued to a faster cache
In the case of a split transaction and a cache that is faster than a
CPU we
could get two responses before next_tick expires. Add an event that is
scheduled in this case and return false rather than asserting.
diffstat:
src/cpu/simple/timing.cc | 11 ++++++++++-
src/cpu/simple/timing.hh | 4 +++-
2 files changed, 13 insertions(+), 2 deletions(-)
diffs (48 lines):
diff -r 9e11081542e4 -r 434b5dfb87d9 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc Mon Nov 15 14:04:03 2010 -0600
+++ b/src/cpu/simple/timing.cc Mon Nov 15 14:04:03 2010 -0600
@@ -999,7 +999,16 @@
if (next_tick == curTick) {
cpu->completeDataAccess(pkt);
} else {
- tickEvent.schedule(pkt, next_tick);
+ if (!tickEvent.scheduled()) {
+ tickEvent.schedule(pkt, next_tick);
+ } else {
+ // In the case of a split transaction and a cache that is
+ // faster than a CPU we could get two responses before
+ // next_tick expires
+ if (!retryEvent.scheduled())
+ schedule(retryEvent, next_tick);
+ return false;
+ }
}
return true;
diff -r 9e11081542e4 -r 434b5dfb87d9 src/cpu/simple/timing.hh
--- a/src/cpu/simple/timing.hh Mon Nov 15 14:04:03 2010 -0600
+++ b/src/cpu/simple/timing.hh Mon Nov 15 14:04:03 2010 -0600
@@ -140,7 +140,7 @@
public:
CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
- : Port(_name, _cpu), cpu(_cpu), lat(_lat)
+ : Port(_name, _cpu), cpu(_cpu), lat(_lat), retryEvent(this)
{ }
bool snoopRangeSent;
@@ -161,12 +161,14 @@
{
PacketPtr pkt;
TimingSimpleCPU *cpu;
+ CpuPort *port;
TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
const char *description() const { return "Timing CPU tick"; }
void schedule(PacketPtr _pkt, Tick t);
};
+ EventWrapper<Port, &Port::sendRetry> retryEvent;
};
class IcachePort : public CpuPort
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