changeset e93e7e0caae1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e93e7e0caae1
description:
CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
diffstat:
src/arch/arm/isa/insts/div.isa | 6 +-
src/arch/arm/isa/insts/fp.isa | 278 ++++++++++-----
src/arch/arm/isa/insts/mult.isa | 6 +-
src/arch/arm/isa/insts/neon.isa | 692 ++++++++++++++++++++-------------------
src/cpu/FuncUnit.py | 17 +
src/cpu/o3/FUPool.py | 2 +-
src/cpu/o3/FuncUnitConfig.py | 35 ++
src/cpu/op_class.hh | 32 +
8 files changed, 634 insertions(+), 434 deletions(-)
diffs (truncated from 2818 to 300 lines):
diff -r cf222bd91228 -r e93e7e0caae1 src/arch/arm/isa/insts/div.isa
--- a/src/arch/arm/isa/insts/div.isa Mon Nov 15 14:04:04 2010 -0600
+++ b/src/arch/arm/isa/insts/div.isa Mon Nov 15 14:04:04 2010 -0600
@@ -56,7 +56,8 @@
'''
sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp",
{ "code": sdivCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "IntDivOp"}, [])
header_output = RegRegRegOpDeclare.subst(sdivIop)
decoder_output = RegRegRegOpConstructor.subst(sdivIop)
exec_output = PredOpExecute.subst(sdivIop)
@@ -77,7 +78,8 @@
'''
udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp",
{ "code": udivCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "IntDivOp"}, [])
header_output += RegRegRegOpDeclare.subst(udivIop)
decoder_output += RegRegRegOpConstructor.subst(udivIop)
exec_output += PredOpExecute.subst(udivIop)
diff -r cf222bd91228 -r e93e7e0caae1 src/arch/arm/isa/insts/fp.isa
--- a/src/arch/arm/isa/insts/fp.isa Mon Nov 15 14:04:04 2010 -0600
+++ b/src/arch/arm/isa/insts/fp.isa Mon Nov 15 14:04:04 2010 -0600
@@ -194,7 +194,8 @@
vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp",
{ "code": vmsrEnabledCheckCode + \
"MiscDest = Op1;",
- "predicate_test": predicateTest },
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" },
["IsSerializeAfter","IsNonSpeculative"])
header_output += FpRegRegOpDeclare.subst(vmsrIop);
decoder_output += FpRegRegOpConstructor.subst(vmsrIop);
@@ -206,15 +207,17 @@
'''
vmsrFpscrIop = InstObjParams("vmsr", "VmsrFpscr", "FpRegRegOp",
{ "code": vmsrFpscrCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop);
decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop);
exec_output += PredOpExecute.subst(vmsrFpscrIop);
vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegOp",
{ "code": vmrsEnabledCheckCode + \
- "Dest = MiscOp1;",
- "predicate_test": predicateTest }, [])
+ "Dest = MiscOp1;",
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegOpDeclare.subst(vmrsIop);
decoder_output += FpRegRegOpConstructor.subst(vmrsIop);
exec_output += PredOpExecute.subst(vmrsIop);
@@ -222,7 +225,8 @@
vmrsFpscrIop = InstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp",
{ "code": vmrsEnabledCheckCode + \
"Dest = Fpscr | FpCondCodes;",
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop);
decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop);
exec_output += PredOpExecute.subst(vmrsFpscrIop);
@@ -232,7 +236,8 @@
'''
vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp",
{ "code": vmrsApsrCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vmrsApsrIop);
decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop);
exec_output += PredOpExecute.subst(vmrsApsrIop);
@@ -243,7 +248,8 @@
'''
vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "FpRegRegImmOp",
{ "code": vmrsApsrFpscrCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vmrsApsrFpscrIop);
decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrFpscrIop);
exec_output += PredOpExecute.subst(vmrsApsrFpscrIop);
@@ -253,7 +259,8 @@
'''
vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp",
{ "code": vmovImmSCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegImmOpDeclare.subst(vmovImmSIop);
decoder_output += FpRegImmOpConstructor.subst(vmovImmSIop);
exec_output += PredOpExecute.subst(vmovImmSIop);
@@ -264,7 +271,8 @@
'''
vmovImmDIop = InstObjParams("vmov", "VmovImmD", "FpRegImmOp",
{ "code": vmovImmDCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegImmOpDeclare.subst(vmovImmDIop);
decoder_output += FpRegImmOpConstructor.subst(vmovImmDIop);
exec_output += PredOpExecute.subst(vmovImmDIop);
@@ -277,7 +285,8 @@
'''
vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "FpRegImmOp",
{ "code": vmovImmQCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegImmOpDeclare.subst(vmovImmQIop);
decoder_output += FpRegImmOpConstructor.subst(vmovImmQIop);
exec_output += PredOpExecute.subst(vmovImmQIop);
@@ -287,7 +296,8 @@
'''
vmovRegSIop = InstObjParams("vmov", "VmovRegS", "FpRegRegOp",
{ "code": vmovRegSCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegOpDeclare.subst(vmovRegSIop);
decoder_output += FpRegRegOpConstructor.subst(vmovRegSIop);
exec_output += PredOpExecute.subst(vmovRegSIop);
@@ -298,7 +308,8 @@
'''
vmovRegDIop = InstObjParams("vmov", "VmovRegD", "FpRegRegOp",
{ "code": vmovRegDCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegOpDeclare.subst(vmovRegDIop);
decoder_output += FpRegRegOpConstructor.subst(vmovRegDIop);
exec_output += PredOpExecute.subst(vmovRegDIop);
@@ -311,7 +322,8 @@
'''
vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp",
{ "code": vmovRegQCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegOpDeclare.subst(vmovRegQIop);
decoder_output += FpRegRegOpConstructor.subst(vmovRegQIop);
exec_output += PredOpExecute.subst(vmovRegQIop);
@@ -321,7 +333,8 @@
'''
vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp",
{ "code": vmovCoreRegBCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegBIop);
decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegBIop);
exec_output += PredOpExecute.subst(vmovCoreRegBIop);
@@ -331,7 +344,8 @@
'''
vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp",
{ "code": vmovCoreRegHCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegHIop);
decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegHIop);
exec_output += PredOpExecute.subst(vmovCoreRegHIop);
@@ -341,7 +355,8 @@
'''
vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp",
{ "code": vmovCoreRegWCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegOpDeclare.subst(vmovCoreRegWIop);
decoder_output += FpRegRegOpConstructor.subst(vmovCoreRegWIop);
exec_output += PredOpExecute.subst(vmovCoreRegWIop);
@@ -352,7 +367,8 @@
'''
vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp",
{ "code": vmovRegCoreUBCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUBIop);
decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUBIop);
exec_output += PredOpExecute.subst(vmovRegCoreUBIop);
@@ -363,7 +379,8 @@
'''
vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp",
{ "code": vmovRegCoreUHCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUHIop);
decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUHIop);
exec_output += PredOpExecute.subst(vmovRegCoreUHIop);
@@ -374,7 +391,8 @@
'''
vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp",
{ "code": vmovRegCoreSBCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSBIop);
decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSBIop);
exec_output += PredOpExecute.subst(vmovRegCoreSBIop);
@@ -385,7 +403,8 @@
'''
vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp",
{ "code": vmovRegCoreSHCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSHIop);
decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSHIop);
exec_output += PredOpExecute.subst(vmovRegCoreSHIop);
@@ -395,7 +414,8 @@
'''
vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp",
{ "code": vmovRegCoreWCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegOpDeclare.subst(vmovRegCoreWIop);
decoder_output += FpRegRegOpConstructor.subst(vmovRegCoreWIop);
exec_output += PredOpExecute.subst(vmovRegCoreWIop);
@@ -406,7 +426,8 @@
'''
vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "FpRegRegRegOp",
{ "code": vmov2Reg2CoreCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop);
decoder_output += FpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop);
exec_output += PredOpExecute.subst(vmov2Reg2CoreIop);
@@ -417,7 +438,8 @@
'''
vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "FpRegRegRegOp",
{ "code": vmov2Core2RegCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "SimdFloatMiscOp" }, [])
header_output += FpRegRegRegOpDeclare.subst(vmov2Core2RegIop);
decoder_output += FpRegRegRegOpConstructor.subst(vmov2Core2RegIop);
exec_output += PredOpExecute.subst(vmov2Core2RegIop);
@@ -454,17 +476,21 @@
fpscr.fz, fpscr.rMode)
'''
- def buildBinFpOp(name, Name, base, singleOp, doubleOp):
+ def buildBinFpOp(name, Name, base, opClass, singleOp, doubleOp):
global header_output, decoder_output, exec_output
code = singleCode % { "op": singleBinOp }
code = code % { "func": singleOp }
sIop = InstObjParams(name + "s", Name + "S", base,
- { "code": code, "predicate_test": predicateTest }, [])
+ { "code": code,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
code = doubleCode % { "op": doubleBinOp }
code = code % { "func": doubleOp }
dIop = InstObjParams(name + "d", Name + "D", base,
- { "code": code, "predicate_test": predicateTest }, [])
+ { "code": code,
+ "predicate_test": predicateTest,
+ "op_class": opClass }, [])
declareTempl = eval(base + "Declare");
constructorTempl = eval(base + "Constructor");
@@ -474,12 +500,16 @@
decoder_output += constructorTempl.subst(iop)
exec_output += PredOpExecute.subst(iop)
- buildBinFpOp("vadd", "Vadd", "FpRegRegRegOp", "fpAddS", "fpAddD")
- buildBinFpOp("vsub", "Vsub", "FpRegRegRegOp", "fpSubS", "fpSubD")
- buildBinFpOp("vdiv", "Vdiv", "FpRegRegRegOp", "fpDivS", "fpDivD")
- buildBinFpOp("vmul", "Vmul", "FpRegRegRegOp", "fpMulS", "fpMulD")
+ buildBinFpOp("vadd", "Vadd", "FpRegRegRegOp", "SimdFloatAddOp", "fpAddS",
+ "fpAddD")
+ buildBinFpOp("vsub", "Vsub", "FpRegRegRegOp", "SimdFloatAddOp", "fpSubS",
+ "fpSubD")
+ buildBinFpOp("vdiv", "Vdiv", "FpRegRegRegOp", "SimdFloatDivOp", "fpDivS",
+ "fpDivD")
+ buildBinFpOp("vmul", "Vmul", "FpRegRegRegOp", "SimdFloatMultOp", "fpMulS",
+ "fpMulD")
- def buildUnaryFpOp(name, Name, base, singleOp, doubleOp = None):
+ def buildUnaryFpOp(name, Name, base, opClass, singleOp, doubleOp = None):
if doubleOp is None:
doubleOp = singleOp
global header_output, decoder_output, exec_output
@@ -487,11 +517,15 @@
code = singleCode % { "op": singleUnaryOp }
code = code % { "func": singleOp }
sIop = InstObjParams(name + "s", Name + "S", base,
- { "code": code, "predicate_test": predicateTest }, [])
+ { "code": code,
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
