changeset 50d219ed2a59 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=50d219ed2a59 description: Regressions: Update regressions for SIMD opclass changes
diffstat: tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini | 166 ++- tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr | 6 + tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout | 10 +- tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 48 +- tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini | 166 ++- tests/long/00.gzip/ref/sparc/linux/o3-timing/simout | 10 +- tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 48 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini | 342 ++++- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr | 4 + tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout | 12 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 88 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini | 178 ++- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr | 4 + tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout | 12 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 48 +- tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini | 166 ++- tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr | 6 + tests/long/30.eon/ref/alpha/tru64/o3-timing/simout | 10 +- tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt | 48 +- tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini | 166 ++- tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr | 6 + tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout | 10 +- tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt | 48 +- tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini | 166 ++- tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr | 6 + tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout | 10 +- tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt | 48 +- tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini | 166 ++- tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr | 6 + tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout | 10 +- tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt | 48 +- tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini | 166 ++- tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr | 6 + tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout | 10 +- tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt | 48 +- tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini | 166 ++- tests/quick/00.hello/ref/alpha/linux/o3-timing/simout | 10 +- tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt | 48 +- tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini | 164 ++- tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr | 2 + tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout | 10 +- tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt | 48 +- tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini | 164 ++- tests/quick/00.hello/ref/mips/linux/o3-timing/simout | 10 +- tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt | 48 +- tests/quick/00.hello/ref/power/linux/o3-timing/config.ini | 164 ++- tests/quick/00.hello/ref/power/linux/o3-timing/simerr | 2 +- tests/quick/00.hello/ref/power/linux/o3-timing/simout | 10 +- tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt | 48 +- tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini | 164 ++- tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout | 10 +- tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt | 88 +- tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini | 164 ++- tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout | 10 +- tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt | 48 +- tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini | 656 ++++++++- tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout | 10 +- tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt | 168 ++- 58 files changed, 3945 insertions(+), 559 deletions(-) diffs (truncated from 6065 to 300 lines): diff -r e93e7e0caae1 -r 50d219ed2a59 tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini Mon Nov 15 14:04:04 2010 -0600 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini Mon Nov 15 14:04:05 2010 -0600 @@ -136,8 +136,8 @@ [system.cpu.fuPool] type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 [system.cpu.fuPool.FUList0] type=FUDesc @@ -231,29 +231,137 @@ [system.cpu.fuPool.FUList5] type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList5.opList +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 -[system.cpu.fuPool.FUList5.opList] +[system.cpu.fuPool.FUList5.opList00] type=OpDesc issueLat=1 -opClass=MemWrite +opClass=SimdAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt opLat=1 [system.cpu.fuPool.FUList6] type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +children=opList +count=0 +opList=system.cpu.fuPool.FUList6.opList -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList6.opList1] +[system.cpu.fuPool.FUList6.opList] type=OpDesc issueLat=1 opClass=MemWrite @@ -261,11 +369,29 @@ [system.cpu.fuPool.FUList7] type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList8] +type=FUDesc children=opList count=1 -opList=system.cpu.fuPool.FUList7.opList +opList=system.cpu.fuPool.FUList8.opList -[system.cpu.fuPool.FUList7.opList] +[system.cpu.fuPool.FUList8.opList] type=OpDesc issueLat=3 opClass=IprAccess @@ -358,7 +484,7 @@ env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff -r e93e7e0caae1 -r 50d219ed2a59 tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr Mon Nov 15 14:04:04 2010 -0600 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr Mon Nov 15 14:04:05 2010 -0600 @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff -r e93e7e0caae1 -r 50d219ed2a59 tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Mon Nov 15 14:04:04 2010 -0600 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Mon Nov 15 14:04:05 2010 -0600 @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 22:21:55 -M5 executing on aus-bc2-b15 +M5 compiled Nov 15 2010 08:52:32 +M5 revision f440cdaf1c2d+ 7743+ default tip +M5 started Nov 15 2010 08:53:40 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff -r e93e7e0caae1 -r 50d219ed2a59 tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Mon Nov 15 14:04:04 2010 -0600 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Mon Nov 15 14:04:05 2010 -0600 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 299092 # Simulator instruction rate (inst/s) -host_mem_usage 240504 # Number of bytes of host memory used -host_seconds 1890.90 # Real time elapsed on the host -host_tick_rate 86086026 # Simulator tick rate (ticks/s) +host_inst_rate 195051 # Simulator instruction rate (inst/s) +host_mem_usage 206584 # Number of bytes of host memory used +host_seconds 2899.51 # Real time elapsed on the host +host_tick_rate 56140502 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated sim_seconds 0.162780 # Number of seconds simulated @@ -281,6 +281,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatMult 5 0.00% 72.62% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.62% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 72.62% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::MemRead 124151932 20.51% 93.13% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::MemWrite 41596836 6.87% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued @@ -298,6 +318,26 @@ system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 73.42% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 73.42% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 73.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 73.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 73.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 73.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 73.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 73.42% # attempts to use FU when none available _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
