changeset 6e399e631a43 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6e399e631a43
description:
ARM: Add comment about the organization of the IT state register
diffstat:
src/arch/arm/miscregs.hh | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diffs (16 lines):
diff -r 50d219ed2a59 -r 6e399e631a43 src/arch/arm/miscregs.hh
--- a/src/arch/arm/miscregs.hh Mon Nov 15 14:04:05 2010 -0600
+++ b/src/arch/arm/miscregs.hh Mon Nov 15 14:04:05 2010 -0600
@@ -262,6 +262,12 @@
EndBitUnion(CPSR)
BitUnion8(ITSTATE)
+ /* Note that the split (cond, mask) below is not as in ARM ARM.
+ * But it is more convenient for simulation. The condition
+ * is always the concatenation of the top 3 bits and the next bit,
+ * which applies when one of the bottom 4 bits is set.
+ * Refer to predecoder.cc for the use case.
+ */
Bitfield<7, 4> cond;
Bitfield<3, 0> mask;
// Bitfields for moving to/from CPSR
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