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Review request for Default. Summary ------- O3: Make the DTLB translateTiming() a split transaction. ISAs that have hardware page table walkers need this. For those ISAs, initiateTranslation can return with NoFault, but with the translation unfinished. In the BaseDynInst::read() function, actual memory(cache) access calling cpu->read() used to occur right after initiateTranslation() function call. This access has been moved to the finishTranslation() so that it occurs when the translation finishes, either by TLB hit or TLB Miss followed by hardware page-walk. Faults occured during translation is detected in finishTranslation() and handled during the IEW stage tick()->handleTranslationFault(). This is a work in progress, but I want to make sure there aren't any issues... Diffs ----- src/arch/arm/tlb.cc 6286bb50127e src/cpu/base_dyn_inst.hh 6286bb50127e src/cpu/base_dyn_inst_impl.hh 6286bb50127e src/cpu/o3/commit_impl.hh 6286bb50127e src/cpu/o3/iew_impl.hh 6286bb50127e src/cpu/o3/lsq.hh 6286bb50127e src/cpu/o3/lsq_impl.hh 6286bb50127e src/cpu/o3/lsq_unit.hh 6286bb50127e src/cpu/o3/lsq_unit_impl.hh 6286bb50127e Diff: http://reviews.m5sim.org/r/321/diff Testing ------- Thanks, Ali
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