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Review request for Default. Summary ------- O3: Change when the memory ordering violation is checked to after dtlb lookup. This patch is a follow-up to the dtlb_timing.patch. Separated intentionally to be understood easily. Dtlb lookup now can finish (finishTranslation()) some time later from the tick it was initiated (initiateAccess()), checking and handling of memory ordering violation needs to happen after finishTranslation() is called for the instruction. The code that handling this violation used to be in executeInsts() has been separated as handleMemOrderViolation(). Also, added cycleMemIssued variable to prevent memory instructions issued in the same cycle are falsely blamed to have caused ordering violation. Diffs ----- src/cpu/base_dyn_inst.hh 6286bb50127e src/cpu/o3/iew.hh 6286bb50127e src/cpu/o3/iew_impl.hh 6286bb50127e src/cpu/o3/lsq_impl.hh 6286bb50127e src/cpu/o3/lsq_unit.hh 6286bb50127e src/cpu/o3/lsq_unit_impl.hh 6286bb50127e Diff: http://reviews.m5sim.org/r/322/diff Testing ------- Thanks, Ali
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