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Generally I like it. I'll trust that the actual mechanism in the commit stage is correct. There are some mostly superficial tweaks that need to happen, but then I'm ok with it. src/arch/sparc/isa/decoder.isa <http://reviews.m5sim.org/r/320/#comment719> This line is probably too long now. src/cpu/o3/commit_impl.hh <http://reviews.m5sim.org/r/320/#comment721> Since this is used in only one spot this intermediate variable probably isn't necessary and obfuscates what's going on a bit. src/cpu/o3/commit_impl.hh <http://reviews.m5sim.org/r/320/#comment720> I'm guessing here, but does commit already have code that does this? Do we want to pull that out into a function? Whether or not this sort of thing is already being done (and I can't imagine it's not) this is a nice mostly independent blob of code doing something fairly specific, so it'd be a great candidate to put in a function and simplify this one. - Gabe On 2010-11-19 16:12:52, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/320/ > ----------------------------------------------------------- > > (Updated 2010-11-19 16:12:52) > > > Review request for Default. > > > Summary > ------- > > O3: Support squashing all state after special instruction > > For SPARC ASIs are added to the ExtMachInst. If the ASI is changed simply > marking the instruction as Serializing isn't enough beacuse that only > stops rename. This provides a mechanism to squash all the instructions > and refetch them > > > Diffs > ----- > > src/arch/sparc/isa/decoder.isa 6286bb50127e > src/cpu/base_dyn_inst.hh 6286bb50127e > src/cpu/o3/commit_impl.hh 6286bb50127e > src/cpu/static_inst.hh 6286bb50127e > > Diff: http://reviews.m5sim.org/r/320/diff > > > Testing > ------- > > > Thanks, > > Ali > >
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