When I was looking up what was supposed to happen with these I saw that IO accesses were supposed to be strongly ordered relative to memory and other IO accesses. Does marking them as uncachable do that? Is there some other special sauce I need to throw in?
Gabe Gabe Black wrote: > changeset 6246338ac1e9 in /z/repo/m5 > details: http://repo.m5sim.org/m5?cmd=changeset;node=6246338ac1e9 > description: > X86: Mark IO space accesses as uncachable. > > diffstat: > > src/arch/x86/tlb.cc | 2 ++ > 1 files changed, 2 insertions(+), 0 deletions(-) > > diffs (19 lines): > > diff -r 0c67ea5dbb7e -r 6246338ac1e9 src/arch/x86/tlb.cc > --- a/src/arch/x86/tlb.cc Mon Nov 22 05:47:54 2010 -0500 > +++ b/src/arch/x86/tlb.cc Mon Nov 22 05:49:03 2010 -0500 > @@ -511,6 +511,7 @@ > req->setFlags(Request::MMAPED_IPR); > req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); > } else if ((IOPort & ~mask(2)) == 0xCFC) { > + req->setFlags(Request::UNCACHEABLE); > Addr configAddress = > tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); > if (bits(configAddress, 31, 31)) { > @@ -519,6 +520,7 @@ > (IOPort & mask(2))); > } > } else { > + req->setFlags(Request::UNCACHEABLE); > req->setPaddr(PhysAddrPrefixIO | IOPort); > } > return NoFault; > _______________________________________________ > m5-dev mailing list > m5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
