changeset a9f9eed35b18 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a9f9eed35b18
description:
ARM: Support switchover with hardware table walkers
diffstat:
src/arch/arm/table_walker.cc | 3 +--
src/arch/arm/tlb.cc | 12 ++++++++++++
src/arch/arm/tlb.hh | 3 +++
src/cpu/base.cc | 21 +++++++++++++++++++++
src/sim/tlb.hh | 6 ++++++
5 files changed, 43 insertions(+), 2 deletions(-)
diffs (109 lines):
diff -r 42da07116e12 -r a9f9eed35b18 src/arch/arm/table_walker.cc
--- a/src/arch/arm/table_walker.cc Wed Dec 01 11:30:04 2010 -0800
+++ b/src/arch/arm/table_walker.cc Tue Dec 07 16:19:57 2010 -0800
@@ -92,8 +92,7 @@
{
if (if_name == "port") {
if (port != NULL)
- fatal("%s: port already connected to %s",
- name(), port->getPeer()->name());
+ return port;
System *sys = params()->sys;
Tick minb = params()->min_backoff;
Tick maxb = params()->max_backoff;
diff -r 42da07116e12 -r a9f9eed35b18 src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc Wed Dec 01 11:30:04 2010 -0800
+++ b/src/arch/arm/tlb.cc Tue Dec 07 16:19:57 2010 -0800
@@ -693,6 +693,18 @@
return fault;
}
+Port*
+TLB::getPort()
+{
+#if FULL_SYSTEM
+ return tableWalker->getPort("port");
+#else
+ return NULL;
+#endif
+}
+
+
+
ArmISA::TLB *
ArmTLBParams::create()
{
diff -r 42da07116e12 -r a9f9eed35b18 src/arch/arm/tlb.hh
--- a/src/arch/arm/tlb.hh Wed Dec 01 11:30:04 2010 -0800
+++ b/src/arch/arm/tlb.hh Tue Dec 07 16:19:57 2010 -0800
@@ -209,6 +209,9 @@
void regStats();
+ // Get the port from the table walker and return it
+ virtual Port *getPort();
+
// Caching misc register values here.
// Writing to misc registers needs to invalidate them.
// translateFunctional/translateSe/translateFs checks if they are
diff -r 42da07116e12 -r a9f9eed35b18 src/cpu/base.cc
--- a/src/cpu/base.cc Wed Dec 01 11:30:04 2010 -0800
+++ b/src/cpu/base.cc Tue Dec 07 16:19:57 2010 -0800
@@ -33,6 +33,7 @@
#include <string>
#include <sstream>
+#include "arch/tlb.hh"
#include "base/cprintf.hh"
#include "base/loader/symtab.hh"
#include "base/misc.hh"
@@ -359,6 +360,26 @@
if (DTRACE(Context))
ThreadContext::compare(oldTC, newTC);
*/
+
+ Port *old_itb_port, *old_dtb_port, *new_itb_port, *new_dtb_port;
+ old_itb_port = oldTC->getITBPtr()->getPort();
+ old_dtb_port = oldTC->getDTBPtr()->getPort();
+ new_itb_port = newTC->getITBPtr()->getPort();
+ new_dtb_port = newTC->getDTBPtr()->getPort();
+
+ // Move over any table walker ports if they exist
+ if (new_itb_port && !new_itb_port->isConnected()) {
+ assert(old_itb_port);
+ Port *peer = old_itb_port->getPeer();;
+ new_itb_port->setPeer(peer);
+ peer->setPeer(new_itb_port);
+ }
+ if (new_dtb_port && !new_dtb_port->isConnected()) {
+ assert(old_dtb_port);
+ Port *peer = old_dtb_port->getPeer();;
+ new_dtb_port->setPeer(peer);
+ peer->setPeer(new_dtb_port);
+ }
}
#if FULL_SYSTEM
diff -r 42da07116e12 -r a9f9eed35b18 src/sim/tlb.hh
--- a/src/sim/tlb.hh Wed Dec 01 11:30:04 2010 -0800
+++ b/src/sim/tlb.hh Tue Dec 07 16:19:57 2010 -0800
@@ -38,6 +38,7 @@
class ThreadContext;
class Packet;
+class Port;
class BaseTLB : public SimObject
{
@@ -52,6 +53,11 @@
public:
virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
+ /** Get any port that the TLB or hardware table walker needs.
+ * This is used for migrating port connections during a takeOverFrom()
+ * call. */
+ virtual Port* getPort() { return NULL; }
+
class Translation
{
public:
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