changeset 9b87755cb699 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9b87755cb699
description:
O3: Support SWAP and predicated loads/store in ARM.
diffstat:
src/arch/arm/isa/insts/swap.isa | 4 +++-
src/cpu/o3/iew.hh | 14 +++++++++++++-
src/cpu/o3/iew_impl.hh | 15 ++++-----------
src/cpu/o3/lsq_unit_impl.hh | 6 +++++-
4 files changed, 25 insertions(+), 14 deletions(-)
diffs (90 lines):
diff -r a9f9eed35b18 -r 9b87755cb699 src/arch/arm/isa/insts/swap.isa
--- a/src/arch/arm/isa/insts/swap.isa Tue Dec 07 16:19:57 2010 -0800
+++ b/src/arch/arm/isa/insts/swap.isa Tue Dec 07 16:19:57 2010 -0800
@@ -65,7 +65,9 @@
(newHeader,
newDecoder,
newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
- self.memFlags, [], base = 'Swap')
+ self.memFlags,
+ ['IsStoreConditional'],
+ base = 'Swap')
header_output += newHeader
decoder_output += newDecoder
exec_output += newExec
diff -r a9f9eed35b18 -r 9b87755cb699 src/cpu/o3/iew.hh
--- a/src/cpu/o3/iew.hh Tue Dec 07 16:19:57 2010 -0800
+++ b/src/cpu/o3/iew.hh Tue Dec 07 16:19:57 2010 -0800
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
@@ -225,7 +237,7 @@
{
if (wbOutstanding-- == wbMax)
ableToIssue = true;
- DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
+ DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn);
assert(wbOutstanding >= 0);
#ifdef DEBUG
assert(wbList.find(sn) != wbList.end());
diff -r a9f9eed35b18 -r 9b87755cb699 src/cpu/o3/iew_impl.hh
--- a/src/cpu/o3/iew_impl.hh Tue Dec 07 16:19:57 2010 -0800
+++ b/src/cpu/o3/iew_impl.hh Tue Dec 07 16:19:57 2010 -0800
@@ -1236,20 +1236,13 @@
fault = ldstQueue.executeStore(inst);
// If the store had a fault then it may not have a mem req
- if (!inst->isStoreConditional() && fault == NoFault) {
- inst->setExecuted();
-
- instToCommit(inst);
- } else if (fault != NoFault) {
- // If the instruction faulted, then we need to send it
along to commit
- // without the instruction completing.
- DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n",
- fault->name(), inst->seqNum);
-
+ if (fault != NoFault || inst->readPredicate() == false ||
+ !inst->isStoreConditional()) {
+ // If the instruction faulted, then we need to send it
along
+ // to commit without the instruction completing.
// Send this instruction to commit, also make sure iew
stage
// realizes there is activity.
inst->setExecuted();
-
instToCommit(inst);
activityThisCycle();
}
diff -r a9f9eed35b18 -r 9b87755cb699 src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh Tue Dec 07 16:19:57 2010 -0800
+++ b/src/cpu/o3/lsq_unit_impl.hh Tue Dec 07 16:19:57 2010 -0800
@@ -531,10 +531,14 @@
Fault store_fault = store_inst->initiateAcc();
if (storeQueue[store_idx].size == 0) {
- DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli],Size = 0\n",
+ DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n",
store_inst->pcState(), store_inst->seqNum);
return store_fault;
+ } else if (store_inst->readPredicate() == false) {
+ DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n",
+ store_inst->seqNum);
+ return store_fault;
}
assert(store_fault == NoFault);
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