changeset 762276cd3cc7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=762276cd3cc7
description:
POWER: Take advantage of new PCState syntax.
diffstat:
src/arch/power/isa/decoder.isa | 36 +++++-----------------------------
src/arch/power/isa/formats/branch.isa | 6 ++--
src/arch/power/isa/operands.isa | 3 +-
3 files changed, 11 insertions(+), 34 deletions(-)
diffs (115 lines):
diff -r 9df469679ac7 -r 762276cd3cc7 src/arch/power/isa/decoder.isa
--- a/src/arch/power/isa/decoder.isa Wed Dec 08 00:27:43 2010 -0800
+++ b/src/arch/power/isa/decoder.isa Wed Dec 08 10:33:03 2010 -0800
@@ -381,20 +381,12 @@
// Conditionally branch relative to PC based on CR and CTR.
format BranchPCRelCondCtr {
- 0: bc({{
- PowerISA::PCState pc = PCS;
- pc.npc((uint32_t)(pc.pc() + disp));
- PCS = pc;
- }});
+ 0: bc({{ NPC = (uint32_t)(PC + disp); }});
}
// Conditionally branch to fixed address based on CR and CTR.
format BranchNonPCRelCondCtr {
- 1: bca({{
- PowerISA::PCState pc = PCS;
- pc.npc(targetAddr);
- PCS = pc;
- }});
+ 1: bca({{ NPC = targetAddr; }});
}
}
@@ -402,20 +394,12 @@
// Unconditionally branch relative to PC.
format BranchPCRel {
- 0: b({{
- PowerISA::PCState pc = PCS;
- pc.npc((uint32_t)(pc.pc() + disp));
- PCS = pc;
- }});
+ 0: b({{ NPC = (uint32_t)(PC + disp); }});
}
// Unconditionally branch to fixed address.
format BranchNonPCRel {
- 1: ba({{
- PowerISA::PCState pc = PCS;
- pc.npc(targetAddr);
- PCS = pc;
- }});
+ 1: ba({{ NPC = targetAddr; }});
}
}
@@ -423,20 +407,12 @@
// Conditionally branch to address in LR based on CR and CTR.
format BranchLrCondCtr {
- 16: bclr({{
- PowerISA::PCState pc = PCS;
- pc.npc(LR & 0xfffffffc);
- PCS = pc;
- }});
+ 16: bclr({{ NPC = LR & 0xfffffffc; }});
}
// Conditionally branch to address in CTR based on CR.
format BranchCtrCond {
- 528: bcctr({{
- PowerISA::PCState pc = PCS;
- pc.npc(CTR & 0xfffffffc);
- PCS = pc;
- }});
+ 528: bcctr({{ NPC = CTR & 0xfffffffc; }});
}
// Condition register manipulation instructions.
diff -r 9df469679ac7 -r 762276cd3cc7 src/arch/power/isa/formats/branch.isa
--- a/src/arch/power/isa/formats/branch.isa Wed Dec 08 00:27:43 2010 -0800
+++ b/src/arch/power/isa/formats/branch.isa Wed Dec 08 10:33:03 2010 -0800
@@ -48,7 +48,7 @@
let {{
# Simple code to update link register (LR).
-updateLrCode = 'PowerISA::PCState lrpc = PCS; LR = lrpc.pc() + 4;'
+updateLrCode = 'LR = PC + 4;'
}};
@@ -105,7 +105,7 @@
cond_code = 'if(condOk(CR)) {\n'
cond_code += ' ' + br_code + '\n'
cond_code += '} else {\n'
- cond_code += ' PCS = PCS;\n'
+ cond_code += ' NPC = NPC;\n'
cond_code += '}\n'
return cond_code
@@ -119,7 +119,7 @@
cond_code += 'if(ctr_ok && cond_ok) {\n'
cond_code += ' ' + br_code + '\n'
cond_code += '} else {\n'
- cond_code += ' PCS = PCS;\n'
+ cond_code += ' NPC = NPC;\n'
cond_code += '}\n'
cond_code += 'CTR = ctr;\n'
return cond_code
diff -r 9df469679ac7 -r 762276cd3cc7 src/arch/power/isa/operands.isa
--- a/src/arch/power/isa/operands.isa Wed Dec 08 00:27:43 2010 -0800
+++ b/src/arch/power/isa/operands.isa Wed Dec 08 10:33:03 2010 -0800
@@ -59,7 +59,8 @@
'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8),
# Program counter and next
- 'PCS': ('PCState', 'uq', None, (None, None, 'IsControl'), 9),
+ 'PC': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 9),
+ 'NPC': ('PCState', 'uw', 'npc', (None, None, 'IsControl'), 9),
# Control registers
'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9),
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