changeset 8ac74e34c6f4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8ac74e34c6f4
description:
MIPS: Take advantage of new PCState syntax.
diffstat:
src/arch/mips/isa/decoder.isa | 42 ++++++++++++-----------------------
src/arch/mips/isa/formats/branch.isa | 26 +++++++--------------
src/arch/mips/isa/operands.isa | 4 ++-
3 files changed, 27 insertions(+), 45 deletions(-)
diffs (216 lines):
diff -r 762276cd3cc7 -r 8ac74e34c6f4 src/arch/mips/isa/decoder.isa
--- a/src/arch/mips/isa/decoder.isa Wed Dec 08 10:33:03 2010 -0800
+++ b/src/arch/mips/isa/decoder.isa Wed Dec 08 10:45:14 2010 -0800
@@ -133,33 +133,29 @@
0x1: jr_hb({{
Config1Reg config1 = Config1;
if (config1.ca == 0) {
- pc.nnpc(Rs);
+ NNPC = Rs;
} else {
panic("MIPS16e not supported\n");
}
- PCS = pc;
}}, IsReturn, ClearHazards);
default: jr({{
Config1Reg config1 = Config1;
if (config1.ca == 0) {
- pc.nnpc(Rs);
+ NNPC = Rs;
} else {
panic("MIPS16e not supported\n");
}
- PCS = pc;
}}, IsReturn);
}
0x1: decode HINT {
0x1: jalr_hb({{
- Rd = pc.nnpc();
- pc.nnpc(Rs);
- PCS = pc;
+ Rd = NNPC;
+ NNPC = Rs;
}}, IsCall, ClearHazards);
default: jalr({{
- Rd = pc.nnpc();
- pc.nnpc(Rs);
- PCS = pc;
+ Rd = NNPC;
+ NNPC = Rs;
}}, IsCall);
}
}
@@ -332,14 +328,9 @@
}
format Jump {
- 0x2: j({{
- pc.nnpc((pc.npc() & 0xF0000000) | (JMPTARG << 2));
- PCS = pc;
- }});
- 0x3: jal({{
- pc.nnpc((pc.npc() & 0xF0000000) | (JMPTARG << 2));
- PCS = pc;
- }}, IsCall, Link);
+ 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }});
+ 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},
+ IsCall, Link);
}
format Branch {
@@ -708,16 +699,15 @@
ConfigReg config = Config;
SRSCtlReg srsCtl = SRSCtl;
DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC);
- MipsISA::PCState pc = PCS;
if (status.erl == 1) {
status.erl = 0;
- pc.npc(ErrorEPC);
+ NPC = ErrorEPC;
// Need to adjust NNPC, otherwise things break
- pc.nnpc(ErrorEPC + sizeof(MachInst));
+ NNPC = ErrorEPC + sizeof(MachInst);
} else {
- pc.npc(EPC);
+ NPC = EPC;
// Need to adjust NNPC, otherwise things break
- pc.nnpc(EPC + sizeof(MachInst));
+ NNPC = EPC + sizeof(MachInst);
status.exl = 0;
if (config.ar >=1 &&
srsCtl.hss > 0 &&
@@ -726,7 +716,6 @@
//xc->setShadowSet(srsCtl.pss);
}
}
- PCS = pc;
LLFlag = 0;
Status = status;
SRSCtl = srsCtl;
@@ -734,15 +723,14 @@
0x1F: deret({{
DebugReg debug = Debug;
- MipsISA::PCState pc = PCS;
if (debug.dm == 1) {
debug.dm = 1;
debug.iexi = 0;
- pc.npc(DEPC);
+ NPC = DEPC;
} else {
+ NPC = NPC;
// Undefined;
}
- PCS = pc;
Debug = debug;
}}, IsReturn, IsSerializing, IsERET);
}
diff -r 762276cd3cc7 -r 8ac74e34c6f4 src/arch/mips/isa/formats/branch.isa
--- a/src/arch/mips/isa/formats/branch.isa Wed Dec 08 10:33:03 2010 -0800
+++ b/src/arch/mips/isa/formats/branch.isa Wed Dec 08 10:45:14 2010 -0800
@@ -225,16 +225,16 @@
}};
def format Branch(code, *opt_flags) {{
- not_taken_code = ''
+ not_taken_code = 'NNPC = NNPC; NPC = NPC;'
#Build Instruction Flags
#Use Link & Likely Flags to Add Link/Condition Code
inst_flags = ('IsDirectControl', )
for x in opt_flags:
if x == 'Link':
- code += 'R31 = pc.nnpc();\n'
+ code += 'R31 = NNPC;\n'
elif x == 'Likely':
- not_taken_code = 'pc.advance();'
+ not_taken_code = 'NNPC = NPC; NPC = PC;'
inst_flags += ('IsCondDelaySlot', )
else:
inst_flags += (x, )
@@ -248,14 +248,12 @@
#Condition code
code = '''
bool cond;
- MipsISA::PCState pc = PCS;
%(code)s
if (cond) {
- pc.nnpc(pc.npc() + disp);
+ NNPC = NPC + disp;
} else {
%(not_taken_code)s
}
- PCS = pc;
''' % { "code" : code, "not_taken_code" : not_taken_code }
iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
@@ -266,16 +264,16 @@
}};
def format DspBranch(code, *opt_flags) {{
- not_taken_code = ''
+ not_taken_code = 'NNPC = NNPC; NPC = NPC;'
#Build Instruction Flags
#Use Link & Likely Flags to Add Link/Condition Code
inst_flags = ('IsDirectControl', )
for x in opt_flags:
if x == 'Link':
- code += 'R32 = pc.nnpc();'
+ code += 'R32 = NNPC;'
elif x == 'Likely':
- not_taken_code = 'pc.advance();'
+ not_taken_code = 'NNPC = NPC, NPC = PC;'
inst_flags += ('IsCondDelaySlot', )
else:
inst_flags += (x, )
@@ -288,16 +286,14 @@
#Condition code
code = '''
- MipsISA::PCState pc = PCS;
bool cond;
uint32_t dspctl = DSPControl;
%(code)s
if (cond) {
- pc.nnpc(pc.npc() + disp);
+ NNPC = NPC + disp;
} else {
%(not_taken_code)s
}
- PCS = pc;
''' % { "code" : code, "not_taken_code" : not_taken_code }
iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
@@ -314,17 +310,13 @@
for x in opt_flags:
if x == 'Link':
code = '''
- R31 = pc.nnpc();
+ R31 = NNPC;
''' + code
elif x == 'ClearHazards':
code += '/* Code Needed to Clear Execute & Inst Hazards */\n'
else:
inst_flags += (x, )
- code = '''
- MipsISA::PCState pc = PCS;
- ''' + code
-
iop = InstObjParams(name, Name, 'Jump', code, inst_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
diff -r 762276cd3cc7 -r 8ac74e34c6f4 src/arch/mips/isa/operands.isa
--- a/src/arch/mips/isa/operands.isa Wed Dec 08 10:33:03 2010 -0800
+++ b/src/arch/mips/isa/operands.isa Wed Dec 08 10:45:14 2010 -0800
@@ -151,5 +151,7 @@
'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
#Program Counter Operands
- 'PCS': ('PCState', 'uw', None, (None, None, 'IsControl'), 4)
+ 'PC': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 4),
+ 'NPC': ('PCState', 'uw', 'npc', (None, None, 'IsControl'), 4),
+ 'NNPC': ('PCState', 'uw', 'nnpc', (None, None, 'IsControl'), 4)
}};
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