> On 2010-12-08 23:39:28, Gabe Black wrote: > > src/cpu/simple/base.cc, line 399 > > <http://reviews.m5sim.org/r/344/diff/1/?file=5467#file5467line399> > > > > The braces are wrong. > > > > Have you tried this with x86? X86_FS? This looks like it will reset the > > predecoder constantly because the pcState is advanced but thread->pcState > > is not. > > > > I don't see how this is the right thing to do if it's not assumed that > > predecoder state (ITSTATE) needs to be updated when branching.
I think I have a better/cleaner fix for this now. Which I'll get Ali to push for consideration in place of this one. - Matt ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/344/#review524 ----------------------------------------------------------- On 2010-12-06 16:12:58, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/344/ > ----------------------------------------------------------- > > (Updated 2010-12-06 16:12:58) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > The CPSR register should only be used for collecting the itstate when the > pipeline is flushed (e.g. init/reset/control flushes). > > > Diffs > ----- > > src/arch/arm/predecoder.hh 2b5fbdcbfb5d > src/arch/arm/predecoder.cc 2b5fbdcbfb5d > src/cpu/simple/base.cc 2b5fbdcbfb5d > > Diff: http://reviews.m5sim.org/r/344/diff > > > Testing > ------- > > > Thanks, > > Ali > >
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