----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/358/#review585 -----------------------------------------------------------
src/mem/ruby/slicc_interface/AbstractCacheEntry.hh <http://reviews.m5sim.org/r/358/#comment823> It looks like you're also changing the lock flag from being a separate table to a cache entry field... this seems reasonable, but also seems independent of the other changes. I don't know that it's worth separating into separate changeset, but there should be some mention of this in the commit message I think. src/mem/slicc/ast/ActionDeclAST.py <http://reviews.m5sim.org/r/358/#comment822> The expression '"%s" % foo' is a pretty unconventional way to force foo to be a string :-). If foo is already a string (which might be the case here) you don't need it at all. If foo is not a string, the conventional way to force a conversion is 'str(foo)'. I see there are a number of places where you do this. - Steve On 2010-12-31 17:50:59, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/358/ > ----------------------------------------------------------- > > (Updated 2010-12-31 17:50:59) > > > Review request for Default. > > > Summary > ------- > > The purpose of this patch is to change the way CacheMemory interfaces with > coherence protocols. Currently, whenever a cache controller (defined in the > protocol under consideration) needs to carry out any operation on a cache > block, it looks up the tag hash map and figures out whether or not the block > exists in the cache. In case it does exist, the operation is carried out > (which requires another lookup). Over a single clock cycle, multiple such > lookups take place as observed through profiling of different protocols. It > was seen that the tag lookup takes anything from 10% to 20% of the simulation > time. In order to reduce this time, this patch is being posted. The > CacheMemory class now will have a function that will return pointer to a > cache block entry, instead of a reference (though the function that returns > the reference has been retained currently). Functions have been introduced > for setting/unsetting a pointer and check its pointer. Similar changes have > been carried out for Transaction Buffer entries as well. > > Note that changes are required to both SLICC and the protocol files. This > patch carries out changes to SLICC and committing this patch alone, I > believe, will ___break___ all the protocols. I am working on patching the > protocols as well. This patch is being put to get feed back from other > developers. > > > Diffs > ----- > > src/mem/protocol/RubySlicc_Types.sm UNKNOWN > src/mem/ruby/slicc_interface/AbstractCacheEntry.hh UNKNOWN > src/mem/ruby/slicc_interface/AbstractCacheEntry.cc UNKNOWN > src/mem/ruby/system/CacheMemory.hh UNKNOWN > src/mem/ruby/system/CacheMemory.cc UNKNOWN > src/mem/ruby/system/TBETable.hh UNKNOWN > src/mem/slicc/ast/ActionDeclAST.py UNKNOWN > src/mem/slicc/ast/FormalParamAST.py UNKNOWN > src/mem/slicc/ast/FuncCallExprAST.py UNKNOWN > src/mem/slicc/ast/FuncDeclAST.py UNKNOWN > src/mem/slicc/ast/InPortDeclAST.py UNKNOWN > src/mem/slicc/ast/IsValidPtrExprAST.py PRE-CREATION > src/mem/slicc/ast/MethodCallExprAST.py UNKNOWN > src/mem/slicc/ast/StaticCastAST.py UNKNOWN > src/mem/slicc/ast/TypeDeclAST.py UNKNOWN > src/mem/slicc/ast/__init__.py UNKNOWN > src/mem/slicc/parser.py UNKNOWN > src/mem/slicc/symbols/StateMachine.py UNKNOWN > src/mem/slicc/symbols/SymbolTable.py UNKNOWN > > Diff: http://reviews.m5sim.org/r/358/diff > > > Testing > ------- > > I have tested these changes using the MOESI_CMP_directory and MI protocols. > > > Thanks, > > Nilay > >
_______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
