1. Below is a snip of a protocol trace that I recently used. I think it is important for us maintain that there is no DPRINTF information prepended to each line. The initial motivation for the protocol trace, was that tracing protocol transitions using standard debug print was too verbose. These traces can be 100’MB if not GBs in size, so reducing the information printed to each line is important. Nilay, could you send a snip of the trace with the patch applied?
2233850 3 L1Cache Load I>IS [0x409ec0, line 0x409ec0] 2233850 3 L1Cache L2_Replacement M>MI [0x40cfc0, line 0x40cfc0] 2233866 3 L1Cache Writeback_Ack MI>I [0x10bd40, line 0x10bd40] 2233866 3 L1Cache Writeback_Ack MI>I [0x40cfc0, line 0x40cfc0] 2234458 3 Seq Done > [0x4033c3, line 0x4033c0] 3380 cycles 2234458 3 L1Cache Exclusive_Data IM>MM_W [0x4033c0, line 0x4033c0] 0Directory-0 2234458 3 Seq Begin > [0x40f883, line 0x40f880] ST 2234459 3 L1Cache All_acks_no_sharers MM_W>MM [0x4033c0, line 0x4033c0] 2234508 3 L1Cache Exclusive_Data IS>M_W [0x409ec0, line 0x409ec0] 0Directory-0 2234509 3 L1Cache All_acks_no_sharers M_W>M [0x409ec0, line 0x409ec0] 2234510 3 L1Cache L1_to_L2 MM>MM [0x4033c0, line 0x4033c0] 2234510 3 L1Cache Load I>IS [0x407ec0, line 0x407ec0] 2234510 3 L1Cache L2_Replacement M>MI [0x40b4c0, line 0x40b4c0] 2234510 3 L1Cache L1_to_L2 M>M [0x409ec0, line 0x409ec0] 2234510 3 L1Cache Load I>IS [0x100c40, line 0x100c40] 2234510 3 L1Cache L2_Replacement MM>MI [0x4033c0, line 0x4033c0] 2. Just for my own knowledge… Nate, you mentioned that handling the SIGABRT signal is the right way to make this feature work for all of M5. Why is that? Is it just the preference not to use macros that overwrite the meaning of assert, or is it something more fundamental? Thanks, Brad From: Nilay Vaish [mailto:ni...@cs.wisc.edu] Sent: Tuesday, January 04, 2011 7:24 PM To: Steve Reinhardt; Ali Saidi; Gabe Black; Nathan Binkert Cc: Nilay Vaish; Default; Beckmann, Brad Subject: Re: Review Request: ruby: get rid of ruby's Debug.hh This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/367/ On January 4th, 2011, 4:31 p.m., Brad Beckmann wrote: Hi Nate, I have a couple questions: 1. Have you looked at the protocol trace output after your change? Does it look exactly like it did before? It seems that the output should be the same based on my brief inspection of your patch, but I would like to be sure about that. It may not be obvious, but there is a specific rational behind the format of the protocol trace and I want to make sure that stays the same. 2. With your patch applied, what happens if one hits an assert when running interactively? Previously, the process would abort allowing one to attach gdb and examine what is going on. I liked that feature and it would be great if we could maintain it. Could we port that feature to all of M5? On January 4th, 2011, 6:05 p.m., Nathan Binkert wrote: 1) I have not, because I don't know how, but I tried hard to make it exactly the same. Can you help me out? It won't look identical because DPRINTF prepends some stuff (curTick and object name) 2) we don't have a mechanism to have the process stall until GDB is attached, but given that this worked in Ruby only, I'd agree that this should be something that we do globally in M5. The right way to do this would be to handle SIGABRT and stall in the abort handler (I think that should work). Can we work on this patch and do that as a separate one? Brad, do you have some protocol trace with you? I have seen the trace that gets generated with the current trace facility using Ruby trace flag. It prints all the events for all the cache controllers and network routers. If you prefer, I can send you an example trace. Or you can generate one by running m5.opt with trace file and trace flag options supplied. ./build/ALPHA_SE_MESI_CMP_directory/m5.opt --trace-file=MESI.trace --trace-flags=Ruby ./configs/example/ruby_random_test.py -l 1000 - Nilay On January 4th, 2011, 3:02 p.m., Nathan Binkert wrote: Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. By Nathan Binkert. Updated 2011-01-04 15:02:38 Description ruby: get rid of ruby's Debug.hh Get rid of the Debug class Get rid of ASSERT and use assert Use DPRINTF for ProtocolTrace Testing This compiles and passes all of the quick regressions, but it would be nice for a Ruby developer to take a look and see if I got rid of any useful functionality. Diffs * configs/ruby/Ruby.py (7338bc628489) * src/mem/SConscript (7338bc628489) * src/mem/ruby/buffers/MessageBuffer.hh (7338bc628489) * src/mem/ruby/buffers/MessageBuffer.cc (7338bc628489) * src/mem/ruby/common/Debug.hh (7338bc628489) * src/mem/ruby/common/Debug.cc (7338bc628489) * src/mem/ruby/common/Debug.py (7338bc628489) * src/mem/ruby/common/Global.hh (7338bc628489) * src/mem/ruby/common/Global.cc (7338bc628489) * src/mem/ruby/common/SConscript (7338bc628489) * src/mem/ruby/common/Set.cc (7338bc628489) * src/mem/ruby/eventqueue/RubyEventQueue.cc (7338bc628489) * src/mem/ruby/filters/BulkBloomFilter.cc (7338bc628489) * src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc (7338bc628489) * src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc (7338bc628489) * src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh (7338bc628489) * src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc (7338bc628489) * src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc (7338bc628489) * src/mem/ruby/network/garnet/flexible-pipeline/flit.hh (7338bc628489) * src/mem/ruby/network/simple/SimpleNetwork.cc (7338bc628489) * src/mem/ruby/network/simple/Throttle.cc (7338bc628489) * src/mem/ruby/network/simple/Topology.cc (7338bc628489) * src/mem/ruby/profiler/Profiler.hh (7338bc628489) * src/mem/ruby/profiler/Profiler.cc (7338bc628489) * src/mem/ruby/slicc_interface/RubySlicc_Util.hh (7338bc628489) * src/mem/ruby/storebuffer/storebuffer.cc (7338bc628489) * src/mem/ruby/system/RubySystem.py (7338bc628489) * src/mem/ruby/system/Sequencer.cc (7338bc628489) * src/mem/ruby/system/System.cc (7338bc628489) * src/mem/ruby/tester/DeterministicDriver.cc (7338bc628489) * src/mem/ruby/tester/RaceyDriver.cc (7338bc628489) * src/mem/ruby/tester/RaceyPseudoThread.cc (7338bc628489) * src/mem/ruby/tester/test_framework.cc (7338bc628489) * src/mem/slicc/symbols/StateMachine.py (7338bc628489) * src/mem/slicc/symbols/Type.py (7338bc628489) View Diff<http://reviews.m5sim.org/r/367/diff/>
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