changeset 19beb0676222 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=19beb0676222
description:
Mem,X86: Make the IO bridge pass APIC messages back towards the CPU.
diffstat:
configs/example/fs.py | 9 ++++++++-
1 files changed, 8 insertions(+), 1 deletions(-)
diffs (19 lines):
diff -r 189b9b258779 -r 19beb0676222 configs/example/fs.py
--- a/configs/example/fs.py Thu Feb 03 20:23:00 2011 -0800
+++ b/configs/example/fs.py Thu Feb 03 20:56:27 2011 -0800
@@ -153,7 +153,14 @@
mem_size = bm[0].mem()
else:
mem_size = SysConfig().mem()
- test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+ # For x86, we need to poke a hole for interrupt messages to get back to the
+ # CPU. These use a portion of the physical address space which has a
+ # non-zero prefix in the top nibble. Normal memory accesses have a 0
+ # prefix.
+ if buildEnv['TARGET_ISA'] == 'x86':
+ test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max >> 4)]
+ else:
+ test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
test_sys.bridge.filter_ranges_b=[AddrRange(mem_size)]
test_sys.iocache = IOCache(addr_range=mem_size)
test_sys.iocache.cpu_side = test_sys.iobus.port
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