changeset 21f14583aa6a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=21f14583aa6a
description:
ARM: Fix bug that let two table walks occur in parallel.
diffstat:
src/arch/arm/table_walker.cc | 8 +++-----
src/arch/arm/tlb.cc | 4 +++-
src/cpu/o3/commit_impl.hh | 2 ++
3 files changed, 8 insertions(+), 6 deletions(-)
diffs (63 lines):
diff -r cb7bf3919bdd -r 21f14583aa6a src/arch/arm/table_walker.cc
--- a/src/arch/arm/table_walker.cc Wed Feb 23 15:10:49 2011 -0600
+++ b/src/arch/arm/table_walker.cc Wed Feb 23 15:10:49 2011 -0600
@@ -141,12 +141,12 @@
if (!currState->timing)
return processWalk();
- if (pending) {
+ if (pending || pendingQueue.size()) {
pendingQueue.push_back(currState);
currState = NULL;
} else {
pending = true;
- processWalk();
+ return processWalk();
}
return NoFault;
@@ -194,10 +194,8 @@
f = tlb->walkTrickBoxCheck(l1desc_addr, currState->vaddr, sizeof(uint32_t),
currState->isFetch, currState->isWrite, 0, true);
if (f) {
+ DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr);
if (currState->timing) {
- currState->transState->finish(f, currState->req,
- currState->tc, currState->mode);
-
pending = false;
nextWalk(currState->tc);
currState = NULL;
diff -r cb7bf3919bdd -r 21f14583aa6a src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc Wed Feb 23 15:10:49 2011 -0600
+++ b/src/arch/arm/tlb.cc Wed Feb 23 15:10:49 2011 -0600
@@ -529,7 +529,7 @@
vaddr, contextId);
fault = tableWalker->walk(req, tc, contextId, mode, translation,
timing);
- if (timing) {
+ if (timing && fault == NoFault) {
delay = true;
// for timing mode, return and wait for table walk
return fault;
@@ -694,6 +694,8 @@
#else
fault = translateSe(req, tc, mode, translation, delay, true);
#endif
+ DPRINTF(TLB, "Translation returning delay=%d fault=%d\n", delay, fault !=
+ NoFault);
if (!delay)
translation->finish(fault, req, tc, mode);
else
diff -r cb7bf3919bdd -r 21f14583aa6a src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh Wed Feb 23 15:10:49 2011 -0600
+++ b/src/cpu/o3/commit_impl.hh Wed Feb 23 15:10:49 2011 -0600
@@ -1142,6 +1142,8 @@
commitStatus[tid] = TrapPending;
+ DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
+ head_inst->seqNum);
if (head_inst->traceData) {
if (DTRACE(ExecFaulting)) {
head_inst->traceData->setFetchSeq(head_inst->seqNum);
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