changeset 749581c26e71 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=749581c26e71
description:
ARM: Do something for ISB, DSB, DMB
diffstat:
src/arch/arm/isa/formats/misc.isa | 9 +++------
src/arch/arm/isa/insts/misc.isa | 11 ++++++++---
src/cpu/o3/commit_impl.hh | 3 ++-
3 files changed, 13 insertions(+), 10 deletions(-)
diffs (73 lines):
diff -r 21f14583aa6a -r 749581c26e71 src/arch/arm/isa/formats/misc.isa
--- a/src/arch/arm/isa/formats/misc.isa Wed Feb 23 15:10:49 2011 -0600
+++ b/src/arch/arm/isa/formats/misc.isa Wed Feb 23 15:10:49 2011 -0600
@@ -120,14 +120,11 @@
return new WarnUnimplemented(
isRead ? "mrc dccmvau" : "mcr dccmvau", machInst);
case MISCREG_CP15ISB:
- return new WarnUnimplemented(
- isRead ? "mrc cp15isb" : "mcr cp15isb", machInst);
+ return new Isb(machInst);
case MISCREG_CP15DSB:
- return new WarnUnimplemented(
- isRead ? "mrc cp15dsb" : "mcr cp15dsb", machInst);
+ return new Dsb(machInst);
case MISCREG_CP15DMB:
- return new WarnUnimplemented(
- isRead ? "mrc cp15dmb" : "mcr cp15dmb", machInst);
+ return new Dmb(machInst);
case MISCREG_ICIALLUIS:
return new WarnUnimplemented(
isRead ? "mrc icialluis" : "mcr icialluis", machInst);
diff -r 21f14583aa6a -r 749581c26e71 src/arch/arm/isa/insts/misc.isa
--- a/src/arch/arm/isa/insts/misc.isa Wed Feb 23 15:10:49 2011 -0600
+++ b/src/arch/arm/isa/insts/misc.isa Wed Feb 23 15:10:49 2011 -0600
@@ -696,19 +696,23 @@
exec_output += ClrexCompleteAcc.subst(clrexIop)
isbCode = '''
+ fault = new FlushPipe;
'''
isbIop = InstObjParams("isb", "Isb", "PredOp",
{"code": isbCode,
- "predicate_test": predicateTest},
['IsSerializing'])
+ "predicate_test": predicateTest},
+ ['IsSerializeAfter'])
header_output += BasicDeclare.subst(isbIop)
decoder_output += BasicConstructor.subst(isbIop)
exec_output += PredOpExecute.subst(isbIop)
dsbCode = '''
+ fault = new FlushPipe;
'''
dsbIop = InstObjParams("dsb", "Dsb", "PredOp",
{"code": dsbCode,
- "predicate_test":
predicateTest},['IsMemBarrier'])
+ "predicate_test": predicateTest},
+ ['IsMemBarrier', 'IsSerializeAfter'])
header_output += BasicDeclare.subst(dsbIop)
decoder_output += BasicConstructor.subst(dsbIop)
exec_output += PredOpExecute.subst(dsbIop)
@@ -717,7 +721,8 @@
'''
dmbIop = InstObjParams("dmb", "Dmb", "PredOp",
{"code": dmbCode,
- "predicate_test":
predicateTest},['IsMemBarrier'])
+ "predicate_test": predicateTest},
+ ['IsMemBarrier'])
header_output += BasicDeclare.subst(dmbIop)
decoder_output += BasicConstructor.subst(dmbIop)
exec_output += PredOpExecute.subst(dmbIop)
diff -r 21f14583aa6a -r 749581c26e71 src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh Wed Feb 23 15:10:49 2011 -0600
+++ b/src/cpu/o3/commit_impl.hh Wed Feb 23 15:10:49 2011 -0600
@@ -1177,7 +1177,8 @@
}
}
#endif
-
+ DPRINTF(Commit, "Committing instruction with [sn:%lli]\n",
+ head_inst->seqNum);
if (head_inst->traceData) {
head_inst->traceData->setFetchSeq(head_inst->seqNum);
head_inst->traceData->setCPSeq(thread[tid]->numInst);
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