changeset af0d29feb39d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=af0d29feb39d
description:
ARM: Squash state on FPSCR stride or len write.
diffstat:
src/arch/arm/isa/insts/fp.isa | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diffs (13 lines):
diff -r a3f5f75db279 -r af0d29feb39d src/arch/arm/isa/insts/fp.isa
--- a/src/arch/arm/isa/insts/fp.isa Wed Feb 23 15:10:49 2011 -0600
+++ b/src/arch/arm/isa/insts/fp.isa Wed Feb 23 15:10:49 2011 -0600
@@ -209,7 +209,8 @@
{ "code": vmsrFpscrCode,
"predicate_test": predicateTest,
"op_class": "SimdFloatMiscOp" },
- ["IsSerializeAfter","IsNonSpeculative"])
+ ["IsSerializeAfter","IsNonSpeculative",
+ "IsSquashAfter"])
header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop);
decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop);
exec_output += PredOpExecute.subst(vmsrFpscrIop);
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