changeset 7bf6fccab013 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7bf6fccab013
description:
O3: If there is an outstanding table walk don't let the inst queue
sleep.
If there is an outstanding table walk and no other activity in the CPU
it can go to sleep and never wake up. This change makes the instruction
queue always active if the CPU is waiting for a store to translate.
If Gabe changes the way this code works then the below should be removed
as indicated by the todo.
diffstat:
src/cpu/o3/inst_queue_impl.hh | 5 ++++-
1 files changed, 4 insertions(+), 1 deletions(-)
diffs (15 lines):
diff -r af0d29feb39d -r 7bf6fccab013 src/cpu/o3/inst_queue_impl.hh
--- a/src/cpu/o3/inst_queue_impl.hh Wed Feb 23 15:10:49 2011 -0600
+++ b/src/cpu/o3/inst_queue_impl.hh Wed Feb 23 15:10:49 2011 -0600
@@ -880,7 +880,10 @@
iqInstsIssued+= total_issued;
// If we issued any instructions, tell the CPU we had activity.
- if (total_issued || total_deferred_mem_issued) {
+ // @todo If the way deferred memory instructions are handeled due to
+ // translation changes then the deferredMemInsts condition should be
removed
+ // from the code below.
+ if (total_issued || total_deferred_mem_issued || deferredMemInsts.size()) {
cpu->activityThisCycle();
} else {
DPRINTF(IQ, "Not able to schedule any instructions.\n");
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
