changeset bba14984f2ce in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bba14984f2ce
description:
ruby: removed unsupported protocol files
diffstat:
src/mem/protocol/MESI_SCMP_bankdirectory-L1cache.sm | 894 -------
src/mem/protocol/MESI_SCMP_bankdirectory-L2cache.sm | 1052 ---------
src/mem/protocol/MESI_SCMP_bankdirectory-mem.sm | 166 -
src/mem/protocol/MESI_SCMP_bankdirectory-msg.sm | 112 -
src/mem/protocol/MESI_SCMP_bankdirectory.slicc | 5 -
src/mem/protocol/MESI_SCMP_bankdirectory_m-mem.sm | 250 --
src/mem/protocol/MESI_SCMP_bankdirectory_m.slicc | 5 -
src/mem/protocol/MOESI_CMP_directory-perfectDir.sm | 573 ----
src/mem/protocol/MOESI_SMP_directory-cache.sm | 981 --------
src/mem/protocol/MOESI_SMP_directory-dir.sm | 495 ----
src/mem/protocol/MOESI_SMP_directory-msg.sm | 89 -
src/mem/protocol/MOESI_SMP_directory.slicc | 4 -
src/mem/protocol/MOESI_SMP_token-cache.sm | 1734 ---------------
src/mem/protocol/MOESI_SMP_token-dir.sm | 405 ---
src/mem/protocol/MOESI_SMP_token-msg.sm | 61 -
src/mem/protocol/MOESI_SMP_token.slicc | 4 -
src/mem/protocol/MOSI_SMP_bcast-cache.sm | 1000 --------
src/mem/protocol/MOSI_SMP_bcast-dir.sm | 267 --
src/mem/protocol/MOSI_SMP_bcast-msg.sm | 79 -
src/mem/protocol/MOSI_SMP_bcast.slicc | 4 -
src/mem/protocol/MOSI_SMP_bcast_1level-cache.sm | 921 -------
src/mem/protocol/MOSI_SMP_bcast_1level.slicc | 4 -
src/mem/protocol/MOSI_SMP_bcast_m-dir.sm | 345 --
src/mem/protocol/MOSI_SMP_bcast_m.slicc | 4 -
src/mem/protocol/MOSI_SMP_directory_1level-cache.sm | 838 -------
src/mem/protocol/MOSI_SMP_directory_1level-dir.sm | 333 --
src/mem/protocol/MOSI_SMP_directory_1level-msg.sm | 74 -
src/mem/protocol/MOSI_SMP_directory_1level.slicc | 4 -
src/mem/protocol/MSI_MOSI_CMP_directory-L1cache.sm | 799 ------
src/mem/protocol/MSI_MOSI_CMP_directory-L2cache.sm | 2191 -------------------
src/mem/protocol/MSI_MOSI_CMP_directory-dir.sm | 497 ----
src/mem/protocol/MSI_MOSI_CMP_directory-msg.sm | 115 -
src/mem/protocol/MSI_MOSI_CMP_directory.slicc | 8 -
src/mem/protocol/standard_1level_SMP-protocol.sm | 39 -
src/mem/protocol/standard_SMP-protocol.sm | 39 -
35 files changed, 0 insertions(+), 14391 deletions(-)
diffs (truncated from 14531 to 300 lines):
diff -r 03ee2388ea9d -r bba14984f2ce
src/mem/protocol/MESI_SCMP_bankdirectory-L1cache.sm
--- a/src/mem/protocol/MESI_SCMP_bankdirectory-L1cache.sm Wed Feb 23
16:35:25 2011 -0500
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,894 +0,0 @@
-
-/*
- * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * $Id: MSI_MOSI_CMP_directory-L1cache.sm 1.10 05/01/19 15:55:40-06:00
beckm...@s0-28.cs.wisc.edu $
- *
- */
-
-
-machine(L1Cache, "MSI Directory L1 Cache CMP") {
-
- // NODE L1 CACHE
- // From this node's L1 cache TO the network
- // a local L1 -> this L2 bank, currently ordered with directory forwarded
requests
- MessageBuffer requestFromL1Cache, network="To", virtual_network="0",
ordered="false";
- // a local L1 -> this L2 bank
- MessageBuffer responseFromL1Cache, network="To", virtual_network="3",
ordered="false";
- MessageBuffer unblockFromL1Cache, network="To", virtual_network="4",
ordered="false";
-
-
- // To this node's L1 cache FROM the network
- // a L2 bank -> this L1
- MessageBuffer requestToL1Cache, network="From", virtual_network="1",
ordered="false";
- // a L2 bank -> this L1
- MessageBuffer responseToL1Cache, network="From", virtual_network="3",
ordered="false";
-
- // STATES
- enumeration(State, desc="Cache states", default="L1Cache_State_I") {
- // Base states
- NP, desc="Not present in either cache";
- I, desc="a L1 cache entry Idle";
- S, desc="a L1 cache entry Shared";
- E, desc="a L1 cache entry Exclusive";
- M, desc="a L1 cache entry Modified", format="!b";
-
- // Transient States
- IS, desc="L1 idle, issued GETS, have not seen response yet";
- IM, desc="L1 idle, issued GETX, have not seen response yet";
- SM, desc="L1 idle, issued GETX, have not seen response yet";
- IS_I, desc="L1 idle, issued GETS, saw Inv before data because directory
doesn't block on GETS hit";
-
- M_I, desc="L1 replacing, waiting for ACK";
- E_I, desc="L1 replacing, waiting for ACK";
-
- }
-
- // EVENTS
- enumeration(Event, desc="Cache events") {
- // L1 events
- Load, desc="Load request from the home processor";
- Ifetch, desc="I-fetch request from the home processor";
- Store, desc="Store request from the home processor";
-
- Inv, desc="Invalidate request from L2 bank";
-
- // internal generated request
- L1_Replacement, desc="L1 Replacement", format="!r";
-
- // other requests
- Fwd_GETX, desc="GETX from other processor";
- Fwd_GETS, desc="GETS from other processor";
- Fwd_GET_INSTR, desc="GET_INSTR from other processor";
-
- Data, desc="Data for processor";
- Data_Exclusive, desc="Data for processor";
- DataS_fromL1, desc="data for GETS request, need to unblock
directory";
- Data_all_Acks, desc="Data for processor, all acks";
-
- Ack, desc="Ack for processor";
- Ack_all, desc="Last ack for processor";
-
- WB_Ack, desc="Ack for replacement";
- }
-
- // TYPES
-
- // CacheEntry
- structure(Entry, desc="...", interface="AbstractCacheEntry" ) {
- State CacheState, desc="cache state";
- DataBlock DataBlk, desc="data for the block";
- bool Dirty, default="false", desc="data is dirty";
- }
-
- // TBE fields
- structure(TBE, desc="...") {
- Address Address, desc="Physical address for this TBE";
- State TBEState, desc="Transient state";
- DataBlock DataBlk, desc="Buffer for the data block";
- bool Dirty, default="false", desc="data is dirty";
- bool isPrefetch, desc="Set if this was caused by a prefetch";
- int pendingAcks, default="0", desc="number of pending acks";
- }
-
- external_type(CacheMemory) {
- bool cacheAvail(Address);
- Address cacheProbe(Address);
- void allocate(Address);
- void deallocate(Address);
- Entry lookup(Address);
- void changePermission(Address, AccessPermission);
- bool isTagPresent(Address);
- }
-
- external_type(TBETable) {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
- }
-
- TBETable L1_TBEs, template_hack="<L1Cache_TBE>";
-
- CacheMemory L1IcacheMemory, template_hack="<L1Cache_Entry>",
constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1I"',
abstract_chip_ptr="true";
- CacheMemory L1DcacheMemory, template_hack="<L1Cache_Entry>",
constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1D"',
abstract_chip_ptr="true";
-
- MessageBuffer mandatoryQueue, ordered="false", rank="100",
abstract_chip_ptr="true";
-
- Sequencer sequencer, abstract_chip_ptr="true", constructor_hack="i";
-
- int cache_state_to_int(State state);
-
- // inclusive cache returns L1 entries only
- Entry getL1CacheEntry(Address addr), return_by_ref="yes" {
- if (L1DcacheMemory.isTagPresent(addr)) {
- return L1DcacheMemory[addr];
- } else {
- return L1IcacheMemory[addr];
- }
- }
-
- void changeL1Permission(Address addr, AccessPermission permission) {
- if (L1DcacheMemory.isTagPresent(addr)) {
- return L1DcacheMemory.changePermission(addr, permission);
- } else if(L1IcacheMemory.isTagPresent(addr)) {
- return L1IcacheMemory.changePermission(addr, permission);
- } else {
- error("cannot change permission, L1 block not present");
- }
- }
-
- bool isL1CacheTagPresent(Address addr) {
- return (L1DcacheMemory.isTagPresent(addr) ||
L1IcacheMemory.isTagPresent(addr));
- }
-
- State getState(Address addr) {
- if((L1DcacheMemory.isTagPresent(addr) &&
L1IcacheMemory.isTagPresent(addr)) == true){
- DEBUG_EXPR(id);
- DEBUG_EXPR(addr);
- }
- assert((L1DcacheMemory.isTagPresent(addr) &&
L1IcacheMemory.isTagPresent(addr)) == false);
-
- if(L1_TBEs.isPresent(addr)) {
- return L1_TBEs[addr].TBEState;
- } else if (isL1CacheTagPresent(addr)) {
- return getL1CacheEntry(addr).CacheState;
- }
- return State:NP;
- }
-
-
- void setState(Address addr, State state) {
- assert((L1DcacheMemory.isTagPresent(addr) &&
L1IcacheMemory.isTagPresent(addr)) == false);
-
- // MUST CHANGE
- if(L1_TBEs.isPresent(addr)) {
- L1_TBEs[addr].TBEState := state;
- }
-
- if (isL1CacheTagPresent(addr)) {
- getL1CacheEntry(addr).CacheState := state;
-
- // Set permission
- if (state == State:I) {
- changeL1Permission(addr, AccessPermission:Invalid);
- } else if (state == State:S || state == State:E) {
- changeL1Permission(addr, AccessPermission:Read_Only);
- } else if (state == State:M) {
- changeL1Permission(addr, AccessPermission:Read_Write);
- } else {
- changeL1Permission(addr, AccessPermission:Busy);
- }
- }
- }
-
- Event mandatory_request_type_to_event(CacheRequestType type) {
- if (type == CacheRequestType:LD) {
- return Event:Load;
- } else if (type == CacheRequestType:IFETCH) {
- return Event:Ifetch;
- } else if ((type == CacheRequestType:ST) || (type ==
CacheRequestType:ATOMIC)) {
- return Event:Store;
- } else {
- error("Invalid CacheRequestType");
- }
- }
-
- GenericMachineType getNondirectHitMachType(Address addr, MachineID sender) {
- if (machineIDToMachineType(sender) == MachineType:L1Cache) {
- return GenericMachineType:L1Cache_wCC; // NOTE direct L1 hits should
not call this
- } else if (machineIDToMachineType(sender) == MachineType:L2Cache) {
- return GenericMachineType:L2Cache;
- } else {
- return ConvertMachToGenericMach(machineIDToMachineType(sender));
- }
- }
-
-
-
- out_port(requestIntraChipL1Network_out, RequestMsg, requestFromL1Cache);
- out_port(responseIntraChipL1Network_out, ResponseMsg, responseFromL1Cache);
- out_port(unblockNetwork_out, ResponseMsg, unblockFromL1Cache);
-
- // Response IntraChip L1 Network - response msg to this L1 cache
- in_port(responseIntraChipL1Network_in, ResponseMsg, responseToL1Cache) {
- if (responseIntraChipL1Network_in.isReady()) {
- peek(responseIntraChipL1Network_in, ResponseMsg) {
- assert(in_msg.Destination.isElement(machineID));
- if(in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
- trigger(Event:Data_Exclusive, in_msg.Address);
- } else if(in_msg.Type == CoherenceResponseType:DATA) {
- if ( (getState(in_msg.Address) == State:IS ||
getState(in_msg.Address) == State:IS_I) &&
- machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache )
{
-
- trigger(Event:DataS_fromL1, in_msg.Address);
-
- } else if ( (L1_TBEs[in_msg.Address].pendingAcks - in_msg.AckCount)
== 0 ) {
- trigger(Event:Data_all_Acks, in_msg.Address);
- } else {
- trigger(Event:Data, in_msg.Address);
- }
- } else if (in_msg.Type == CoherenceResponseType:ACK) {
- if ( (L1_TBEs[in_msg.Address].pendingAcks - in_msg.AckCount) == 0 ) {
- trigger(Event:Ack_all, in_msg.Address);
- } else {
- trigger(Event:Ack, in_msg.Address);
- }
- } else if (in_msg.Type == CoherenceResponseType:WB_ACK) {
- trigger(Event:WB_Ack, in_msg.Address);
- } else {
- error("Invalid L1 response type");
- }
- }
- }
- }
-
- // Request InterChip network - request from this L1 cache to the shared L2
- in_port(requestIntraChipL1Network_in, RequestMsg, requestToL1Cache) {
- if(requestIntraChipL1Network_in.isReady()) {
- peek(requestIntraChipL1Network_in, RequestMsg) {
- assert(in_msg.Destination.isElement(machineID));
- if (in_msg.Type == CoherenceRequestType:INV) {
- trigger(Event:Inv, in_msg.Address);
- } else if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type ==
CoherenceRequestType:UPGRADE) {
- // upgrade transforms to GETX due to race
- trigger(Event:Fwd_GETX, in_msg.Address);
- } else if (in_msg.Type == CoherenceRequestType:GETS) {
- trigger(Event:Fwd_GETS, in_msg.Address);
- } else if (in_msg.Type == CoherenceRequestType:GET_INSTR) {
- trigger(Event:Fwd_GET_INSTR, in_msg.Address);
- } else {
- error("Invalid forwarded request type");
- }
- }
- }
- }
-
- // Mandatory Queue betweens Node's CPU and it's L1 caches
- in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
- if (mandatoryQueue_in.isReady()) {
- peek(mandatoryQueue_in, CacheMsg) {
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