changeset d1bb88080be4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d1bb88080be4
description:
ruby: cleaned up access permission enum
diffstat:
src/mem/protocol/MESI_CMP_directory-L2cache.sm | 2 +-
src/mem/protocol/RubySlicc_Exports.sm | 20 +++++++++++++-------
src/mem/ruby/slicc_interface/AbstractCacheEntry.cc | 3 +--
src/mem/ruby/system/PerfectCacheMemory.hh | 2 +-
4 files changed, 16 insertions(+), 11 deletions(-)
diffs (68 lines):
diff -r bba14984f2ce -r d1bb88080be4
src/mem/protocol/MESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm Wed Feb 23 16:41:26
2011 -0800
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm Wed Feb 23 16:41:58
2011 -0800
@@ -219,7 +219,7 @@
} else if (state == State:M) {
cache_entry.changePermission(AccessPermission:Read_Write);
} else if (state == State:MT) {
- cache_entry.changePermission(AccessPermission:Stale);
+ cache_entry.changePermission(AccessPermission:Invalid);
} else {
cache_entry.changePermission(AccessPermission:Busy);
}
diff -r bba14984f2ce -r d1bb88080be4 src/mem/protocol/RubySlicc_Exports.sm
--- a/src/mem/protocol/RubySlicc_Exports.sm Wed Feb 23 16:41:26 2011 -0800
+++ b/src/mem/protocol/RubySlicc_Exports.sm Wed Feb 23 16:41:58 2011 -0800
@@ -47,14 +47,20 @@
// Declarations of external types that are common to all protocols
// AccessPermission
+// The following five states define the access permission of all memory blocks.
+// These permissions have multiple uses. They coordinate locking and
+// synchronization primitives, as well as enable functional accesses.
+// One should not need to add any additional permission values and it is very
+// risky to do so.
enumeration(AccessPermission, desc="...",
default="AccessPermission_NotPresent") {
- Busy, desc="No Read or Write";
- Read_Only, desc="Read Only";
- Read_Write, desc="Read/Write";
- Invalid, desc="Invalid";
- NotPresent, desc="NotPresent";
- ReadUpgradingToWrite, desc="Read only, but trying to get Read/Write";
- Stale, desc="local L1 has a modified copy, assume L2 copy is stale
data";
+ // Valid data
+ Read_Only, desc="block is Read Only (modulo functional writes)";
+ Read_Write, desc="block is Read/Write";
+
+ // Invalid data
+ Invalid, desc="block is in an Invalid base state";
+ NotPresent, desc="block is NotPresent";
+ Busy, desc="block is in a transient state, currently invalid";
}
// TesterStatus
diff -r bba14984f2ce -r d1bb88080be4
src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc Wed Feb 23
16:41:26 2011 -0800
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc Wed Feb 23
16:41:58 2011 -0800
@@ -50,8 +50,7 @@
{
m_Permission = new_perm;
if ((new_perm == AccessPermission_Invalid) ||
- (new_perm == AccessPermission_NotPresent) ||
- (new_perm == AccessPermission_Stale)) {
+ (new_perm == AccessPermission_NotPresent)) {
m_locked = -1;
}
}
diff -r bba14984f2ce -r d1bb88080be4 src/mem/ruby/system/PerfectCacheMemory.hh
--- a/src/mem/ruby/system/PerfectCacheMemory.hh Wed Feb 23 16:41:26 2011 -0800
+++ b/src/mem/ruby/system/PerfectCacheMemory.hh Wed Feb 23 16:41:58 2011 -0800
@@ -149,7 +149,7 @@
PerfectCacheMemory<ENTRY>::allocate(const Address& address)
{
PerfectCacheLineState<ENTRY> line_state;
- line_state.m_permission = AccessPermission_Busy;
+ line_state.m_permission = AccessPermission_Invalid;
line_state.m_entry = ENTRY();
m_map[line_address(address)] = line_state;
}
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
