changeset bf0335d98250 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bf0335d98250
description:
ruby: automate permission setting
This patch integrates permissions with cache and memory states, and then
automates the setting of permissions within the generated code. No
longer
does one need to manually set the permissions within the setState
funciton.
This patch will faciliate easier functional access support by always
correctly
setting permissions for both cache and memory states.
diffstat:
src/mem/protocol/MESI_CMP_directory-L1cache.sm | 37 ++----
src/mem/protocol/MESI_CMP_directory-L2cache.sm | 49 +++-----
src/mem/protocol/MESI_CMP_directory-dir.sm | 22 +-
src/mem/protocol/MESI_CMP_directory-dma.sm | 8 +-
src/mem/protocol/MI_example-cache.sm | 21 +--
src/mem/protocol/MI_example-dir.sm | 22 +-
src/mem/protocol/MI_example-dma.sm | 8 +-
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 46 ++-----
src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 125 ++++++++++----------
src/mem/protocol/MOESI_CMP_directory-dir.sm | 36 +++---
src/mem/protocol/MOESI_CMP_directory-dma.sm | 8 +-
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 53 +++-----
src/mem/protocol/MOESI_CMP_token-L2cache.sm | 27 +---
src/mem/protocol/MOESI_CMP_token-dir.sm | 34 ++--
src/mem/protocol/MOESI_CMP_token-dma.sm | 8 +-
src/mem/protocol/MOESI_hammer-cache.sm | 61 +++------
src/mem/protocol/MOESI_hammer-dir.sm | 56 ++++----
src/mem/protocol/MOESI_hammer-dma.sm | 10 +-
src/mem/protocol/RubySlicc_Types.sm | 4 +-
src/mem/ruby/slicc_interface/AbstractCacheEntry.cc | 10 +-
src/mem/ruby/slicc_interface/AbstractCacheEntry.hh | 5 +-
src/mem/ruby/slicc_interface/AbstractEntry.cc | 13 ++
src/mem/ruby/slicc_interface/AbstractEntry.hh | 7 +
src/mem/slicc/ast/StateDeclAST.py | 79 +++++++++++++
src/mem/slicc/ast/TypeFieldEnumAST.py | 9 +-
src/mem/slicc/ast/TypeFieldStateAST.py | 61 ++++++++++
src/mem/slicc/ast/__init__.py | 2 +
src/mem/slicc/parser.py | 20 +++
src/mem/slicc/symbols/StateMachine.py | 13 ++
src/mem/slicc/symbols/Type.py | 40 ++++++
30 files changed, 514 insertions(+), 380 deletions(-)
diffs (truncated from 1395 to 300 lines):
diff -r d1eb504fd302 -r bf0335d98250
src/mem/protocol/MESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm Wed Feb 23 16:41:58
2011 -0800
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm Wed Feb 23 16:41:59
2011 -0800
@@ -52,23 +52,23 @@
MessageBuffer responseToL1Cache, network="From", virtual_network="1",
ordered="false";
// STATES
- enumeration(State, desc="Cache states", default="L1Cache_State_I") {
+ state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
// Base states
- NP, desc="Not present in either cache";
- I, desc="a L1 cache entry Idle";
- S, desc="a L1 cache entry Shared";
- E, desc="a L1 cache entry Exclusive";
- M, desc="a L1 cache entry Modified", format="!b";
+ NP, AccessPermission:Invalid, desc="Not present in either cache";
+ I, AccessPermission:Invalid, desc="a L1 cache entry Idle";
+ S, AccessPermission:Read_Only, desc="a L1 cache entry Shared";
+ E, AccessPermission:Read_Only, desc="a L1 cache entry Exclusive";
+ M, AccessPermission:Read_Write, desc="a L1 cache entry Modified",
format="!b";
// Transient States
- IS, desc="L1 idle, issued GETS, have not seen response yet";
- IM, desc="L1 idle, issued GETX, have not seen response yet";
- SM, desc="L1 idle, issued GETX, have not seen response yet";
- IS_I, desc="L1 idle, issued GETS, saw Inv before data because directory
doesn't block on GETS hit";
+ IS, AccessPermission:Busy, desc="L1 idle, issued GETS, have not seen
response yet";
+ IM, AccessPermission:Busy, desc="L1 idle, issued GETX, have not seen
response yet";
+ SM, AccessPermission:Read_Only, desc="L1 idle, issued GETX, have not seen
response yet";
+ IS_I, AccessPermission:Busy, desc="L1 idle, issued GETS, saw Inv before
data because directory doesn't block on GETS hit";
- M_I, desc="L1 replacing, waiting for ACK";
- E_I, desc="L1 replacing, waiting for ACK";
- SINK_WB_ACK, desc="This is to sink WB_Acks from L2";
+ M_I, AccessPermission:Busy, desc="L1 replacing, waiting for ACK";
+ E_I, AccessPermission:Busy, desc="L1 replacing, waiting for ACK";
+ SINK_WB_ACK, AccessPermission:Busy, desc="This is to sink WB_Acks from L2";
}
@@ -180,17 +180,6 @@
if (is_valid(cache_entry)) {
cache_entry.CacheState := state;
-
- // Set permission
- if (state == State:I) {
- cache_entry.changePermission(AccessPermission:Invalid);
- } else if (state == State:S || state == State:E) {
- cache_entry.changePermission(AccessPermission:Read_Only);
- } else if (state == State:M) {
- cache_entry.changePermission(AccessPermission:Read_Write);
- } else {
- cache_entry.changePermission(AccessPermission:Busy);
- }
}
}
diff -r d1eb504fd302 -r bf0335d98250
src/mem/protocol/MESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm Wed Feb 23 16:41:58
2011 -0800
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm Wed Feb 23 16:41:59
2011 -0800
@@ -51,33 +51,33 @@
// MessageBuffer unblockToL2Cache, network="From", virtual_network="4",
ordered="false"; // a local L1 || Memory -> this L2 bank
// STATES
- enumeration(State, desc="L2 Cache states", default="L2Cache_State_NP") {
+ state_declaration(State, desc="L2 Cache states", default="L2Cache_State_NP")
{
// Base states
- NP, desc="Not present in either cache";
- SS, desc="L2 cache entry Shared, also present in one or more L1s";
- M, desc="L2 cache entry Modified, not present in any L1s", format="!b";
- MT, desc="L2 cache entry Modified in a local L1, assume L2 copy stale",
format="!b";
+ NP, AccessPermission:Invalid, desc="Not present in either cache";
+ SS, AccessPermission:Read_Only, desc="L2 cache entry Shared, also present
in one or more L1s";
+ M, AccessPermission:Read_Write, desc="L2 cache entry Modified, not present
in any L1s", format="!b";
+ MT, AccessPermission:Invalid, desc="L2 cache entry Modified in a local L1,
assume L2 copy stale", format="!b";
// L2 replacement
- M_I, desc="L2 cache replacing, have all acks, sent dirty data to memory,
waiting for ACK from memory";
- MT_I, desc="L2 cache replacing, getting data from exclusive";
- MCT_I, desc="L2 cache replacing, clean in L2, getting data or ack from
exclusive";
- I_I, desc="L2 replacing clean data, need to inv sharers and then drop
data";
- S_I, desc="L2 replacing dirty data, collecting acks from L1s";
+ M_I, AccessPermission:Busy, desc="L2 cache replacing, have all acks, sent
dirty data to memory, waiting for ACK from memory";
+ MT_I, AccessPermission:Busy, desc="L2 cache replacing, getting data from
exclusive";
+ MCT_I, AccessPermission:Busy, desc="L2 cache replacing, clean in L2,
getting data or ack from exclusive";
+ I_I, AccessPermission:Busy, desc="L2 replacing clean data, need to inv
sharers and then drop data";
+ S_I, AccessPermission:Busy, desc="L2 replacing dirty data, collecting acks
from L1s";
// Transient States for fetching data from memory
- ISS, desc="L2 idle, got single L1_GETS, issued memory fetch, have not seen
response yet";
- IS, desc="L2 idle, got L1_GET_INSTR or multiple L1_GETS, issued memory
fetch, have not seen response yet";
- IM, desc="L2 idle, got L1_GETX, issued memory fetch, have not seen
response(s) yet";
+ ISS, AccessPermission:Busy, desc="L2 idle, got single L1_GETS, issued
memory fetch, have not seen response yet";
+ IS, AccessPermission:Busy, desc="L2 idle, got L1_GET_INSTR or multiple
L1_GETS, issued memory fetch, have not seen response yet";
+ IM, AccessPermission:Busy, desc="L2 idle, got L1_GETX, issued memory
fetch, have not seen response(s) yet";
// Blocking states
- SS_MB, desc="Blocked for L1_GETX from SS";
- MT_MB, desc="Blocked for L1_GETX from MT";
- M_MB, desc="Blocked for L1_GETX from M";
+ SS_MB, AccessPermission:Busy, desc="Blocked for L1_GETX from SS";
+ MT_MB, AccessPermission:Busy, desc="Blocked for L1_GETX from MT";
+ M_MB, AccessPermission:Busy, desc="Blocked for L1_GETX from M";
- MT_IIB, desc="Blocked for L1_GETS from MT, waiting for unblock and data";
- MT_IB, desc="Blocked for L1_GETS from MT, got unblock, waiting for data";
- MT_SB, desc="Blocked for L1_GETS from MT, got data, waiting for unblock";
+ MT_IIB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, waiting
for unblock and data";
+ MT_IB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got
unblock, waiting for data";
+ MT_SB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got data,
waiting for unblock";
}
@@ -212,17 +212,6 @@
if (is_valid(cache_entry)) {
cache_entry.CacheState := state;
-
- // Set permission
- if (state == State:SS ) {
- cache_entry.changePermission(AccessPermission:Read_Only);
- } else if (state == State:M) {
- cache_entry.changePermission(AccessPermission:Read_Write);
- } else if (state == State:MT) {
- cache_entry.changePermission(AccessPermission:Invalid);
- } else {
- cache_entry.changePermission(AccessPermission:Busy);
- }
}
}
diff -r d1eb504fd302 -r bf0335d98250 src/mem/protocol/MESI_CMP_directory-dir.sm
--- a/src/mem/protocol/MESI_CMP_directory-dir.sm Wed Feb 23 16:41:58
2011 -0800
+++ b/src/mem/protocol/MESI_CMP_directory-dir.sm Wed Feb 23 16:41:59
2011 -0800
@@ -49,19 +49,19 @@
MessageBuffer responseFromDir, network="To", virtual_network="1",
ordered="false";
// STATES
- enumeration(State, desc="Directory states", default="Directory_State_I") {
+ state_declaration(State, desc="Directory states",
default="Directory_State_I") {
// Base states
- I, desc="Owner";
- ID, desc="Intermediate state for DMA_READ when in I";
- ID_W, desc="Intermediate state for DMA_WRITE when in I";
+ I, AccessPermission:Read_Write, desc="dir is the owner and memory is
up-to-date, all other copies are Invalid";
+ ID, AccessPermission:Busy, desc="Intermediate state for DMA_READ when in
I";
+ ID_W, AccessPermission:Busy, desc="Intermediate state for DMA_WRITE when
in I";
- M, desc="Modified";
- IM, desc="Intermediate State I>M";
- MI, desc="Intermediate State M>I";
- M_DRD, desc="Intermediate State when there is a dma read";
- M_DRDI, desc="Intermediate State when there is a dma read";
- M_DWR, desc="Intermediate State when there is a dma write";
- M_DWRI, desc="Intermediate State when there is a dma write";
+ M, AccessPermission:Invalid, desc="memory copy may be stale, i.e. other
modified copies may exist";
+ IM, AccessPermission:Busy, desc="Intermediate State I>M";
+ MI, AccessPermission:Busy, desc="Intermediate State M>I";
+ M_DRD, AccessPermission:Busy, desc="Intermediate State when there is a dma
read";
+ M_DRDI, AccessPermission:Busy, desc="Intermediate State when there is a
dma read";
+ M_DWR, AccessPermission:Busy, desc="Intermediate State when there is a dma
write";
+ M_DWRI, AccessPermission:Busy, desc="Intermediate State when there is a
dma write";
}
// Events
diff -r d1eb504fd302 -r bf0335d98250 src/mem/protocol/MESI_CMP_directory-dma.sm
--- a/src/mem/protocol/MESI_CMP_directory-dma.sm Wed Feb 23 16:41:58
2011 -0800
+++ b/src/mem/protocol/MESI_CMP_directory-dma.sm Wed Feb 23 16:41:59
2011 -0800
@@ -7,10 +7,10 @@
MessageBuffer responseFromDir, network="From", virtual_network="1",
ordered="true", no_vector="true";
MessageBuffer reqToDirectory, network="To", virtual_network="0",
ordered="false", no_vector="true";
- enumeration(State, desc="DMA states", default="DMA_State_READY") {
- READY, desc="Ready to accept a new request";
- BUSY_RD, desc="Busy: currently processing a request";
- BUSY_WR, desc="Busy: currently processing a request";
+ state_declaration(State, desc="DMA states", default="DMA_State_READY") {
+ READY, AccessPermission:Invalid, desc="Ready to accept a new request";
+ BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a
request";
+ BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a
request";
}
enumeration(Event, desc="DMA events") {
diff -r d1eb504fd302 -r bf0335d98250 src/mem/protocol/MI_example-cache.sm
--- a/src/mem/protocol/MI_example-cache.sm Wed Feb 23 16:41:58 2011 -0800
+++ b/src/mem/protocol/MI_example-cache.sm Wed Feb 23 16:41:59 2011 -0800
@@ -14,15 +14,15 @@
MessageBuffer responseToCache, network="From", virtual_network="4",
ordered="true";
// STATES
- enumeration(State, desc="Cache states") {
- I, desc="Not Present/Invalid";
- II, desc="Not Present/Invalid, issued PUT";
- M, desc="Modified";
- MI, desc="Modified, issued PUT";
- MII, desc="Modified, issued PUTX, received nack";
+ state_declaration(State, desc="Cache states") {
+ I, AccessPermission:Invalid, desc="Not Present/Invalid";
+ II, AccessPermission:Busy, desc="Not Present/Invalid, issued PUT";
+ M, AccessPermission:Read_Write, desc="Modified";
+ MI, AccessPermission:Busy, desc="Modified, issued PUT";
+ MII, AccessPermission:Busy, desc="Modified, issued PUTX, received nack";
- IS, desc="Issued request for LOAD/IFETCH";
- IM, desc="Issued request for STORE/ATOMIC";
+ IS, AccessPermission:Busy, desc="Issued request for LOAD/IFETCH";
+ IM, AccessPermission:Busy, desc="Issued request for STORE/ATOMIC";
}
// EVENTS
@@ -117,11 +117,6 @@
if (is_valid(cache_entry)) {
cache_entry.CacheState := state;
- if (state == State:M) {
- cache_entry.changePermission(AccessPermission:Read_Write);
- } else {
- cache_entry.changePermission(AccessPermission:Invalid);
- }
}
}
diff -r d1eb504fd302 -r bf0335d98250 src/mem/protocol/MI_example-dir.sm
--- a/src/mem/protocol/MI_example-dir.sm Wed Feb 23 16:41:58 2011 -0800
+++ b/src/mem/protocol/MI_example-dir.sm Wed Feb 23 16:41:59 2011 -0800
@@ -13,21 +13,21 @@
MessageBuffer dmaRequestToDir, network="From", virtual_network="0",
ordered="true";
// STATES
- enumeration(State, desc="Directory states", default="Directory_State_I") {
+ state_declaration(State, desc="Directory states",
default="Directory_State_I") {
// Base states
- I, desc="Invalid";
- M, desc="Modified";
+ I, AccessPermission:Read_Write, desc="Invalid";
+ M, AccessPermission:Invalid, desc="Modified";
- M_DRD, desc="Blocked on an invalidation for a DMA read";
- M_DWR, desc="Blocked on an invalidation for a DMA write";
+ M_DRD, AccessPermission:Busy, desc="Blocked on an invalidation for a DMA
read";
+ M_DWR, AccessPermission:Busy, desc="Blocked on an invalidation for a DMA
write";
- M_DWRI, desc="Intermediate state M_DWR-->I";
- M_DRDI, desc="Intermediate state M_DRD-->I";
+ M_DWRI, AccessPermission:Busy, desc="Intermediate state M_DWR-->I";
+ M_DRDI, AccessPermission:Busy, desc="Intermediate state M_DRD-->I";
- IM, desc="Intermediate state I-->M";
- MI, desc="Intermediate state M-->I";
- ID, desc="Intermediate state for DMA_READ when in I";
- ID_W, desc="Intermediate state for DMA_WRITE when in I";
+ IM, AccessPermission:Busy, desc="Intermediate state I-->M";
+ MI, AccessPermission:Busy, desc="Intermediate state M-->I";
+ ID, AccessPermission:Busy, desc="Intermediate state for DMA_READ when in
I";
+ ID_W, AccessPermission:Busy, desc="Intermediate state for DMA_WRITE when
in I";
}
// Events
diff -r d1eb504fd302 -r bf0335d98250 src/mem/protocol/MI_example-dma.sm
--- a/src/mem/protocol/MI_example-dma.sm Wed Feb 23 16:41:58 2011 -0800
+++ b/src/mem/protocol/MI_example-dma.sm Wed Feb 23 16:41:59 2011 -0800
@@ -7,10 +7,10 @@
MessageBuffer responseFromDir, network="From", virtual_network="1",
ordered="true", no_vector="true";
MessageBuffer reqToDirectory, network="To", virtual_network="0",
ordered="false", no_vector="true";
- enumeration(State, desc="DMA states", default="DMA_State_READY") {
- READY, desc="Ready to accept a new request";
- BUSY_RD, desc="Busy: currently processing a request";
- BUSY_WR, desc="Busy: currently processing a request";
+ state_declaration(State, desc="DMA states", default="DMA_State_READY") {
+ READY, AccessPermission:Invalid, desc="Ready to accept a new request";
+ BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a
request";
+ BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a
request";
}
enumeration(Event, desc="DMA events") {
diff -r d1eb504fd302 -r bf0335d98250
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Wed Feb 23 16:41:58
2011 -0800
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Wed Feb 23 16:41:59
2011 -0800
@@ -58,25 +58,25 @@
// STATES
- enumeration(State, desc="Cache states", default="L1Cache_State_I") {
+ state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
// Base states
- I, desc="Idle";
- S, desc="Shared";
- O, desc="Owned";
- M, desc="Modified (dirty)";
- M_W, desc="Modified (dirty)";
- MM, desc="Modified (dirty and locally modified)";
- MM_W, desc="Modified (dirty and locally modified)";
+ I, AccessPermission:Invalid, desc="Idle";
+ S, AccessPermission:Read_Only, desc="Shared";
+ O, AccessPermission:Read_Only, desc="Owned";
+ M, AccessPermission:Read_Only, desc="Modified (dirty)";
+ M_W, AccessPermission:Read_Only, desc="Modified (dirty)";
+ MM, AccessPermission:Read_Write, desc="Modified (dirty and locally
modified)";
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