changeset d1eb504fd302 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d1eb504fd302
description:
MOESI_hammer: cache probe address clean up
diffstat:
src/mem/protocol/MOESI_hammer-cache.sm | 46 +++++++++++++++++++--------------
src/mem/slicc/ast/LocalVariableAST.py | 9 +++++-
2 files changed, 33 insertions(+), 22 deletions(-)
diffs (116 lines):
diff -r d1bb88080be4 -r d1eb504fd302 src/mem/protocol/MOESI_hammer-cache.sm
--- a/src/mem/protocol/MOESI_hammer-cache.sm Wed Feb 23 16:41:58 2011 -0800
+++ b/src/mem/protocol/MOESI_hammer-cache.sm Wed Feb 23 16:41:58 2011 -0800
@@ -390,10 +390,11 @@
if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) {
trigger(Event:L1_to_L2, in_msg.LineAddress, L1Dcache_entry,
tbe);
} else {
+ Address l2_victim_addr :=
L2cacheMemory.cacheProbe(in_msg.LineAddress);
trigger(Event:L2_Replacement,
- L2cacheMemory.cacheProbe(in_msg.LineAddress),
-
getL2CacheEntry(L2cacheMemory.cacheProbe(in_msg.LineAddress)),
- TBEs[L2cacheMemory.cacheProbe(in_msg.LineAddress)]);
+ l2_victim_addr,
+ getL2CacheEntry(l2_victim_addr),
+ TBEs[l2_victim_addr]);
}
}
@@ -412,18 +413,20 @@
}
} else {
// No room in the L1, so we need to make room
- if
(L2cacheMemory.cacheAvail(L1IcacheMemory.cacheProbe(in_msg.LineAddress))) {
+ Address l1i_victim_addr :=
L1IcacheMemory.cacheProbe(in_msg.LineAddress);
+ if (L2cacheMemory.cacheAvail(l1i_victim_addr)) {
// The L2 has room, so we move the line from the L1 to the L2
trigger(Event:L1_to_L2,
- L1IcacheMemory.cacheProbe(in_msg.LineAddress),
-
getL1ICacheEntry(L1IcacheMemory.cacheProbe(in_msg.LineAddress)),
- TBEs[L1IcacheMemory.cacheProbe(in_msg.LineAddress)]);
+ l1i_victim_addr,
+ getL1ICacheEntry(l1i_victim_addr),
+ TBEs[l1i_victim_addr]);
} else {
+ Address l2_victim_addr :=
L2cacheMemory.cacheProbe(l1i_victim_addr);
// The L2 does not have room, so we replace a line from the L2
trigger(Event:L2_Replacement,
-
L2cacheMemory.cacheProbe(L1IcacheMemory.cacheProbe(in_msg.LineAddress)),
-
getL2CacheEntry(L2cacheMemory.cacheProbe(L1IcacheMemory.cacheProbe(in_msg.LineAddress))),
-
TBEs[L2cacheMemory.cacheProbe(L1IcacheMemory.cacheProbe(in_msg.LineAddress))]);
+ l2_victim_addr,
+ getL2CacheEntry(l2_victim_addr),
+ TBEs[l2_victim_addr]);
}
}
}
@@ -444,10 +447,11 @@
if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) {
trigger(Event:L1_to_L2, in_msg.LineAddress, L1Icache_entry,
tbe);
} else {
+ Address l2_victim_addr :=
L2cacheMemory.cacheProbe(in_msg.LineAddress);
trigger(Event:L2_Replacement,
- L2cacheMemory.cacheProbe(in_msg.LineAddress),
-
getL2CacheEntry(L2cacheMemory.cacheProbe(in_msg.LineAddress)),
- TBEs[L2cacheMemory.cacheProbe(in_msg.LineAddress)]);
+ l2_victim_addr,
+ getL2CacheEntry(l2_victim_addr),
+ TBEs[l2_victim_addr]);
}
}
@@ -465,18 +469,20 @@
}
} else {
// No room in the L1, so we need to make room
- if
(L2cacheMemory.cacheAvail(L1DcacheMemory.cacheProbe(in_msg.LineAddress))) {
+ Address l1d_victim_addr :=
L1DcacheMemory.cacheProbe(in_msg.LineAddress);
+ if (L2cacheMemory.cacheAvail(l1d_victim_addr)) {
// The L2 has room, so we move the line from the L1 to the L2
trigger(Event:L1_to_L2,
- L1DcacheMemory.cacheProbe(in_msg.LineAddress),
-
getL1DCacheEntry(L1DcacheMemory.cacheProbe(in_msg.LineAddress)),
- TBEs[L1DcacheMemory.cacheProbe(in_msg.LineAddress)]);
+ l1d_victim_addr,
+ getL1DCacheEntry(l1d_victim_addr),
+ TBEs[l1d_victim_addr]);
} else {
+ Address l2_victim_addr :=
L2cacheMemory.cacheProbe(l1d_victim_addr);
// The L2 does not have room, so we replace a line from the L2
trigger(Event:L2_Replacement,
-
L2cacheMemory.cacheProbe(L1DcacheMemory.cacheProbe(in_msg.LineAddress)),
-
getL2CacheEntry(L2cacheMemory.cacheProbe(L1DcacheMemory.cacheProbe(in_msg.LineAddress))),
-
TBEs[L2cacheMemory.cacheProbe(L1DcacheMemory.cacheProbe(in_msg.LineAddress))]);
+ l2_victim_addr,
+ getL2CacheEntry(l2_victim_addr),
+ TBEs[l2_victim_addr]);
}
}
}
diff -r d1bb88080be4 -r d1eb504fd302 src/mem/slicc/ast/LocalVariableAST.py
--- a/src/mem/slicc/ast/LocalVariableAST.py Wed Feb 23 16:41:58 2011 -0800
+++ b/src/mem/slicc/ast/LocalVariableAST.py Wed Feb 23 16:41:58 2011 -0800
@@ -30,10 +30,11 @@
from slicc.symbols import Var
class LocalVariableAST(StatementAST):
- def __init__(self, slicc, type_ast, ident):
+ def __init__(self, slicc, type_ast, ident, pointer = False):
super(LocalVariableAST, self).__init__(slicc)
self.type_ast = type_ast
self.ident = ident
+ self.pointer = pointer
def __repr__(self):
return "[LocalVariableAST: %r %r]" % (self.type_ast, self.ident)
@@ -50,5 +51,9 @@
v = Var(self.symtab, self.ident, self.location, type, ident,
self.pairs)
self.symtab.newSymbol(v)
- code += "%s* %s" % (type.c_ident, ident)
+ if self.pointer or str(type) == "TBE" or (
+ "interface" in type and type["interface"] == "AbstractCacheEntry"):
+ code += "%s* %s" % (type.c_ident, ident)
+ else:
+ code += "%s %s" % (type.c_ident, ident)
return type
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