My recollection is that there was one memory mapped IPR in Alpha and
that we dealt with it in the TLB by swallowing the request. If you
actually want that to get sent out somewhere, it should just be
uncacheable and be swallowed at the point where it is used. I 10
second check of the code indicates that this code may have been
removed for alpha though since I see an UnimpFault("IPR memory space
not implemented")
Nate
On Thu, Feb 24, 2011 at 3:34 AM, Gabe Black <[email protected]> wrote:
> I'm making some progress getting X86_FS working in O3, and now I'm
> running into a problem where it looks like a memory mapped register,
> specifically a segment base register, isn't being handled properly. It
> looks like the access is actually going to memory instead of being
> redirected to the control register. Some other weird things may be going
> on as well since the value being written is wrong but shows up in the
> disassembly correctly, and only one write happens when in the simple CPU
> there are two. Maybe store coalescing of some sort? I dug around in O3's
> source a bit and couldn't find anywhere the memory mapped IPR flag was
> being checked, so O3 may be oblivious to this sort of thing. That's
> surprising since I -thought- it already supported that. In retrospect I
> don't know that I had any good reason to think that. I think you added
> that mechanism, Ali. Any idea what's going on? Will I have to implement
> that support?
>
> Gabe
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>
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