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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary ------- ARM: Allow conditional quiesce instructions. This patch prevents not executed conditional instructions marked as IsQuiesce from stalling the pipeline indefinitely. If the instruction is not executed the quiesceSkip psuedoinst is called which schedules a wakes up call to the fetch stage. Diffs ----- src/arch/arm/isa/insts/m5ops.isa 5138d1e453f1 src/arch/arm/isa/insts/misc.isa 5138d1e453f1 src/arch/arm/isa/templates/pred.isa 5138d1e453f1 src/sim/pseudo_inst.hh 5138d1e453f1 src/sim/pseudo_inst.cc 5138d1e453f1 Diff: http://reviews.m5sim.org/r/569/diff Testing ------- Thanks, Ali _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
