> On 2011-03-11 18:58:46, Gabe Black wrote: > > Why are you fixing up the fact that the CPU shouldn't have quiesced instead > > of preventing it from doing it in the first place? If the instruction is > > being executed speculatively, you should mark it as non-speculative. If O3 > > is basing its behavior off of the instruction's flags instead of its > > behavior (ie. if it actually called quiesce), I'd argue it shouldn't be > > doing that.
Because for the CPU to quiesce it needs to stall early (in fetch) and it does so by testing the IsQuiesce flag of the instruction. Even if it's not speculative that doesn't solve the problem for us if the instruction is predicated false. So after we end up processing the instruction if it was predicated false we need to wake up the fetch stage which had just quiesced. > On 2011-03-11 18:58:46, Gabe Black wrote: > > src/arch/arm/isa/insts/misc.isa, line 498 > > <http://reviews.m5sim.org/r/569/diff/1/?file=10834#file10834line498> > > > > This should be on the same line as the } k > On 2011-03-11 18:58:46, Gabe Black wrote: > > src/sim/pseudo_inst.hh, line 48 > > <http://reviews.m5sim.org/r/569/diff/1/?file=10836#file10836line48> > > > > This isn't really a pseudo instruction at all, it's a generic call to > > fix up a pseudo instruction that should never have been called. well, it's the most logical place for the code given what it does. - Ali ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/569/#review945 ----------------------------------------------------------- On 2011-03-11 15:20:18, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/569/ > ----------------------------------------------------------- > > (Updated 2011-03-11 15:20:18) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > ARM: Allow conditional quiesce instructions. > > This patch prevents not executed conditional instructions marked as > IsQuiesce from stalling the pipeline indefinitely. If the instruction > is not executed the quiesceSkip psuedoinst is called which schedules a > wakes up call to the fetch stage. > > > Diffs > ----- > > src/arch/arm/isa/insts/m5ops.isa 5138d1e453f1 > src/arch/arm/isa/insts/misc.isa 5138d1e453f1 > src/arch/arm/isa/templates/pred.isa 5138d1e453f1 > src/sim/pseudo_inst.hh 5138d1e453f1 > src/sim/pseudo_inst.cc 5138d1e453f1 > > Diff: http://reviews.m5sim.org/r/569/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
