> On 2011-03-16 15:17:00, Gabe Black wrote: > > There are a number of style issues to clean up, but otherwise this seems > > mostly ok. I'm still not crazy about having an mt.hh that's only used in > > InOrder and MIPS, as far as I'm aware. That's ISA specific behavior > > masquerading as something generic, but that's probably a separate issue > > from this change.
Agreed on the mt.hh file, I've been thinking of ways to mask that out. I need to double check, but if those are just per-thread RegFile calls are just triggered through instruction calls then maybe the ISA description can handle it. > On 2011-03-16 15:17:00, Gabe Black wrote: > > src/arch/sparc/registers.hh, line 80 > > <http://reviews.m5sim.org/r/583/diff/2/?file=10956#file10956line80> > > > > This seems redundant. Can't the CPU model add them up just as easily? The CPU Model could calculate these but it would be the same line wherever you put it. I'm not sure it's redundant though, since there isn't necessarily a constant that just encapsulates all the registers available and there other places throughout the code where we are adding constants together to make a easy generic term to use for other objects to draw form. Overall, I thought this was the right place because all the register dependency tracking and sizing of Register Files basically uses this file's constants. - Korey ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/583/#review967 ----------------------------------------------------------- On 2011-03-14 17:39:33, Korey Sewell wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/583/ > ----------------------------------------------------------- > > (Updated 2011-03-14 17:39:33) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > sparc: compilation fixes for inorder > Add a few constants and functions that the InOrder model wants for SPARC. > * * * > sparc: add eaComp function > InOrder separates the address generation from the actual access so give > Sparc that functionality > * * * > sparc: add control flags for branches > branch predictors and other cpu model functions need to know specific > information > about branches, so add the necessary flags here > > > Diffs > ----- > > src/arch/sparc/isa/decoder.isa 6c9b532da0a6 > src/arch/sparc/isa/formats/branch.isa 6c9b532da0a6 > src/arch/sparc/isa/formats/mem/basicmem.isa 6c9b532da0a6 > src/arch/sparc/isa/formats/mem/swap.isa 6c9b532da0a6 > src/arch/sparc/isa/formats/mem/util.isa 6c9b532da0a6 > src/arch/sparc/mt.hh PRE-CREATION > src/arch/sparc/registers.hh 6c9b532da0a6 > src/cpu/inorder/cpu.cc 6c9b532da0a6 > src/cpu/inorder/inorder_dyn_inst.cc 6c9b532da0a6 > > Diff: http://reviews.m5sim.org/r/583/diff > > > Testing > ------- > > > Thanks, > > Korey > > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
