> On 2011-04-13 13:43:26, Gabe Black wrote: > > Please fix these style issues, including the ones in this file I haven't > > explicitly pointed out. You should be using M5 style generally, but > > especially when your in M5 code. Also, please be sure to point this out to > > one of the classic memory system experts (Nate, Steve, or Ali) and get them > > to sign off. They might not see that this change touches outside of Ruby.
Gabe, I made the changes that you had pointed. - Nilay ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/611/#review1113 ----------------------------------------------------------- On 2011-04-13 14:29:01, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/611/ > ----------------------------------------------------------- > > (Updated 2011-04-13 14:29:01) > > > Review request for Default. > > > Summary > ------- > > Ruby: Add support for functional accesses > This patch is meant for implementing functional access support in Ruby. > Currently, the patch does not functional accesses for the PioPort. > > > Diffs > ----- > > configs/example/ruby_mem_test.py 8b5f900233ee > configs/ruby/MESI_CMP_directory.py 8b5f900233ee > configs/ruby/Ruby.py 8b5f900233ee > src/cpu/testers/memtest/memtest.cc 8b5f900233ee > src/mem/packet.hh 8b5f900233ee > src/mem/packet.cc 8b5f900233ee > src/mem/protocol/MESI_CMP_directory-L1cache.sm 8b5f900233ee > src/mem/protocol/MESI_CMP_directory-L2cache.sm 8b5f900233ee > src/mem/protocol/MESI_CMP_directory-dir.sm 8b5f900233ee > src/mem/protocol/RubySlicc_Types.sm 8b5f900233ee > src/mem/ruby/network/Network.cc 8b5f900233ee > src/mem/ruby/network/Network.py 8b5f900233ee > src/mem/ruby/profiler/Profiler.cc 8b5f900233ee > src/mem/ruby/profiler/Profiler.py 8b5f900233ee > src/mem/ruby/recorder/Tracer.cc 8b5f900233ee > src/mem/ruby/recorder/Tracer.py 8b5f900233ee > src/mem/ruby/system/AbstractMemory.hh PRE-CREATION > src/mem/ruby/system/AbstractMemory.cc PRE-CREATION > src/mem/ruby/system/AbstractMemory.py PRE-CREATION > src/mem/ruby/system/Cache.py 8b5f900233ee > src/mem/ruby/system/CacheMemory.hh 8b5f900233ee > src/mem/ruby/system/CacheMemory.cc 8b5f900233ee > src/mem/ruby/system/DirectoryMemory.hh 8b5f900233ee > src/mem/ruby/system/DirectoryMemory.cc 8b5f900233ee > src/mem/ruby/system/DirectoryMemory.py 8b5f900233ee > src/mem/ruby/system/RubyPort.hh 8b5f900233ee > src/mem/ruby/system/RubyPort.cc 8b5f900233ee > src/mem/ruby/system/RubySystem.py 8b5f900233ee > src/mem/ruby/system/SConscript 8b5f900233ee > src/mem/ruby/system/Sequencer.cc 8b5f900233ee > src/mem/ruby/system/Sequencer.py 8b5f900233ee > src/mem/ruby/system/System.hh 8b5f900233ee > src/mem/ruby/system/System.cc 8b5f900233ee > src/mem/slicc/ast/MemberExprAST.py 8b5f900233ee > > Diff: http://reviews.m5sim.org/r/611/diff > > > Testing > ------- > > I have tested functional accesses with the ratio between functional > and timing accesses for different ratios -- 100:0, 99:1, 90:1, 50:50, > 10:90, 1:99. It is working in all the cases. > > > Thanks, > > Nilay > > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
