I'm certain that I compiled the whole tree with debug, opt, and fast, in addition to running regressions. I pretty much do that every time. What I must not have done was compile all of the different coherence protocols though (I didn't realize that more were run in regressions since I last updated my script). Why don't we make opt the default for util/regress if that's the right thing to do? Of course, then I may forget to compile fast and have bugs due to that. Running both opt and fast on regress every time would fix it, but the number of variants that we need to compile is getting ridiculous. We need to figure out a way to compile multiple coherence protocols into a single binary and probably compile SE and FS into the same binary.
Nate > This has to do with DPRINTFs in Ruby code, so I think it's related to > Nate's recent changes. Note that the regressions pass because they > run with m5.fast which compiles out DPRINTFs. I'm pretty sure I've > said this before, but I think we should run regressions with opt and > not fast (at least some of the time). Certainly people should run > regressions with opt and not just fast before they commit, since this > also gives the opportunity to catch run-time assertions. > > Steve > > > % util/regress -k --variant=debug > [...] > [ CXX] > ALPHA_SE_MESI_CMP_directory/mem/protocol/L2Cache_L1Cache_request_type_to_event.cc > -> .do > build/ALPHA_SE_MESI_CMP_directory/mem/protocol/L2Cache_L1Cache_request_type_to_event.cc: > In member function 'L2Cache_Event > L2Cache_Controller::L2Cache_L1Cache_request_type_to_event(CoherenceRequestType, > Address, MachineID, L2Cache_Entry*)': > build/ALPHA_SE_MESI_CMP_directory/mem/protocol/L2Cache_L1Cache_request_type_to_event.cc:32: > error: 'RubySlicc' is not a member of 'Debug' > scons: *** > [build/ALPHA_SE_MESI_CMP_directory/mem/protocol/L2Cache_L1Cache_request_type_to_event.do] > Error 1 > [ CXX] ALPHA_SE_MESI_CMP_directory/mem/protocol/L2Cache_addSharer.cc -> > .do > build/ALPHA_SE_MESI_CMP_directory/mem/protocol/L2Cache_addSharer.cc: > In member function 'void > L2Cache_Controller::L2Cache_addSharer(Address, MachineID, > L2Cache_Entry*)': > build/ALPHA_SE_MESI_CMP_directory/mem/protocol/L2Cache_addSharer.cc:23: > error: 'RubySlicc' is not a member of 'Debug' > scons: *** > [build/ALPHA_SE_MESI_CMP_directory/mem/protocol/L2Cache_addSharer.do] > Error 1 > scons: `build/ALPHA_SE_MOESI_CMP_directory/m5.debug' is up to date. > [ CXX] > ALPHA_SE_MOESI_CMP_token/mem/protocol/L1Cache_averageLatencyEstimate.cc > -> .do > build/ALPHA_SE_MOESI_CMP_token/mem/protocol/L1Cache_averageLatencyEstimate.cc: > In member function 'int > L1Cache_Controller::L1Cache_averageLatencyEstimate()': > build/ALPHA_SE_MOESI_CMP_token/mem/protocol/L1Cache_averageLatencyEstimate.cc:9: > error: 'RubySlicc' is not a member of 'Debug' > scons: *** > [build/ALPHA_SE_MOESI_CMP_token/mem/protocol/L1Cache_averageLatencyEstimate.do] > Error 1 > [ CXX] > ALPHA_SE_MOESI_CMP_token/mem/protocol/L1Cache_updateAverageLatencyEstimate.cc > -> .do > build/ALPHA_SE_MOESI_CMP_token/mem/protocol/L1Cache_updateAverageLatencyEstimate.cc: > In member function 'void > L1Cache_Controller::L1Cache_updateAverageLatencyEstimate(int)': > build/ALPHA_SE_MOESI_CMP_token/mem/protocol/L1Cache_updateAverageLatencyEstimate.cc:9: > error: 'RubySlicc' is not a member of 'Debug' > scons: *** > [build/ALPHA_SE_MOESI_CMP_token/mem/protocol/L1Cache_updateAverageLatencyEstimate.do] > Error 1 > [ CXX] > ALPHA_SE_MOESI_CMP_token/mem/protocol/L2Cache_convertToGenericType.cc > -> .do > build/ALPHA_SE_MOESI_CMP_token/mem/protocol/L2Cache_convertToGenericType.cc: > In member function 'GenericRequestType > L2Cache_Controller::L2Cache_convertToGenericType(CoherenceRequestType)': > build/ALPHA_SE_MOESI_CMP_token/mem/protocol/L2Cache_convertToGenericType.cc:15: > error: 'RubySlicc' is not a member of 'Debug' > scons: *** > [build/ALPHA_SE_MOESI_CMP_token/mem/protocol/L2Cache_convertToGenericType.do] > Error 1 > _______________________________________________ > m5-dev mailing list > m5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
