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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary ------- ARM: Further break up condition code into NZ, C, V bits. Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect dependencies between instructions. Diffs ----- src/arch/arm/faults.cc 5a9a639ce16f src/arch/arm/intregs.hh 5a9a639ce16f src/arch/arm/isa/formats/fp.isa 5a9a639ce16f src/arch/arm/isa/formats/pred.isa 5a9a639ce16f src/arch/arm/isa/insts/data.isa 5a9a639ce16f src/arch/arm/isa/insts/fp.isa 5a9a639ce16f src/arch/arm/isa/insts/ldr.isa 5a9a639ce16f src/arch/arm/isa/insts/macromem.isa 5a9a639ce16f src/arch/arm/isa/insts/mem.isa 5a9a639ce16f src/arch/arm/isa/insts/misc.isa 5a9a639ce16f src/arch/arm/isa/insts/mult.isa 5a9a639ce16f src/arch/arm/isa/insts/str.isa 5a9a639ce16f src/arch/arm/isa/operands.isa 5a9a639ce16f src/arch/arm/isa/templates/pred.isa 5a9a639ce16f src/arch/arm/isa/templates/vfp.isa 5a9a639ce16f src/arch/arm/miscregs.hh 5a9a639ce16f src/arch/arm/nativetrace.cc 5a9a639ce16f src/arch/arm/utility.hh 5a9a639ce16f Diff: http://reviews.m5sim.org/r/681/diff Testing ------- Thanks, Ali _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
