changeset 3824fbc8ed9a in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=3824fbc8ed9a description: ARM: Update ARM_FS stats for mp changes
diffstat: tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini | 25 +- tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr | 6 - tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout | 6 +- tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt | 920 +++++----- tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt | 16 +- tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt | 16 +- tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 16 +- tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt | 16 +- tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini | 25 +- tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr | 6 - tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout | 6 +- tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt | 306 +- tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini | 25 +- tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr | 6 - tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout | 6 +- tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt | 398 ++-- 16 files changed, 913 insertions(+), 886 deletions(-) diffs (truncated from 2795 to 300 lines): diff -r 45f3ac6b6a1c -r 3824fbc8ed9a tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini Wed May 04 20:38:28 2011 -0500 +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini Wed May 04 20:38:28 2011 -0500 @@ -9,12 +9,17 @@ type=LinuxArmSystem children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver boot_cpu_frequency=500 +boot_loader= +boot_loader_mem=Null boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0 +flags_addr=0 +gic_cpu_addr=0 init_param=0 kernel=/chips/pd/randd/dist/binaries/vmlinux.arm load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing +midr_regval=890236928 physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -547,7 +552,7 @@ two_queue=false write_buffers=8 cpu_side=system.iobus.port[25] -mem_side=system.membus.port[5] +mem_side=system.membus.port[6] [system.l2c] type=BaseCache @@ -579,7 +584,7 @@ two_queue=false write_buffers=8 cpu_side=system.toL2Bus.port[0] -mem_side=system.membus.port[6] +mem_side=system.membus.port[7] [system.membus] type=Bus @@ -591,7 +596,7 @@ use_default_range=false width=64 default=system.membus.badaddr_responder.pio -port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.iocache.mem_side system.l2c.mem_side +port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -621,10 +626,18 @@ [system.realview] type=RealView -children=aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake intrctrl=system.intrctrl system=system +[system.realview.a9scu] +type=A9SCU +pio_addr=520093696 +pio_latency=1000 +platform=system.realview +system=system +pio=system.membus.port[5] + [system.realview.aaci_fake] type=AmbaFake amba_id=0 @@ -721,7 +734,7 @@ type=IsaFake pio_addr=1073741824 pio_latency=1000 -pio_size=67108864 +pio_size=536870912 platform=system.realview ret_bad_addr=false ret_data16=65535 @@ -739,6 +752,7 @@ cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +int_latency=10000 it_lines=128 platform=system.realview system=system @@ -830,6 +844,7 @@ [system.realview.realview_io] type=RealViewCtrl +idreg=0 pio_addr=268435456 pio_latency=1000 platform=system.realview diff -r 45f3ac6b6a1c -r 3824fbc8ed9a tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr Wed May 04 20:38:28 2011 -0500 +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr Wed May 04 20:38:28 2011 -0500 @@ -8,16 +8,12 @@ For more information see: http://www.m5sim.org/warn/23a3c326 warn: The csselr register isn't implemented. For more information see: http://www.m5sim.org/warn/c0c486b8 -warn: Need to flush all TLBs in MP -For more information see: http://www.m5sim.org/warn/6cccf999 warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb warn: The ccsidr register isn't implemented and always reads as 0. For more information see: http://www.m5sim.org/warn/2c4acb9c warn: instruction 'mcr dccimvac' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb -warn: Need to flush all TLBs in MP -For more information see: http://www.m5sim.org/warn/6cccf999 warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb warn: instruction 'mcr dccmvau' unimplemented @@ -36,8 +32,6 @@ For more information see: http://www.m5sim.org/warn/21b09adb warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb -warn: Need to flush all TLBs in MP -For more information see: http://www.m5sim.org/warn/6cccf999 warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb hack: be nice to actually delete the event here diff -r 45f3ac6b6a1c -r 3824fbc8ed9a tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout Wed May 04 20:38:28 2011 -0500 +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout Wed May 04 20:38:28 2011 -0500 @@ -5,11 +5,11 @@ All Rights Reserved -M5 compiled May 1 2011 21:51:08 -M5 started May 1 2011 21:52:01 +M5 compiled May 2 2011 15:06:32 +M5 started May 2 2011 15:06:36 M5 executing on u200439-lin.austin.arm.com command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 82642207500 because m5_exit instruction encountered +Exiting @ tick 82662703500 because m5_exit instruction encountered diff -r 45f3ac6b6a1c -r 3824fbc8ed9a tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt Wed May 04 20:38:28 2011 -0500 +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt Wed May 04 20:38:28 2011 -0500 @@ -1,389 +1,389 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 118050 # Simulator instruction rate (inst/s) -host_mem_usage 388868 # Number of bytes of host memory used -host_seconds 439.34 # Real time elapsed on the host -host_tick_rate 188104852 # Simulator tick rate (ticks/s) +host_inst_rate 157394 # Simulator instruction rate (inst/s) +host_mem_usage 389256 # Number of bytes of host memory used +host_seconds 329.61 # Real time elapsed on the host +host_tick_rate 250791706 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 51864248 # Number of instructions simulated -sim_seconds 0.082642 # Number of seconds simulated -sim_ticks 82642207500 # Number of ticks simulated +sim_insts 51877985 # Number of instructions simulated +sim_seconds 0.082663 # Number of seconds simulated +sim_ticks 82662703500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 9217139 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 11723346 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 156768 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 663592 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 11213737 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 13194323 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 788661 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 639897 # The number of times a branch was mispredicted -system.cpu.commit.branches 8427507 # Number of branches committed -system.cpu.commit.bw_lim_events 797883 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 9219891 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 11725604 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 157156 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 663969 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 11218057 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 13199466 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 789166 # Number of times the RAS was used to get a target. +system.cpu.commit.branchMispredicts 640286 # The number of times a branch was mispredicted +system.cpu.commit.branches 8429112 # Number of branches committed +system.cpu.commit.bw_lim_events 798153 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 51987478 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 2962739 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 16084299 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 93469913 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.556195 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.349609 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 52001215 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 2962888 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 16092788 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 93510390 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.556101 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.349439 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 71838189 76.86% 76.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 10610207 11.35% 88.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3480363 3.72% 91.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1644006 1.76% 93.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3523448 3.77% 97.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 741299 0.79% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 540450 0.58% 98.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 294068 0.31% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 797883 0.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 71869411 76.86% 76.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 10616143 11.35% 88.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3483966 3.73% 91.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1643130 1.76% 93.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3524025 3.77% 97.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 741321 0.79% 98.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 539866 0.58% 98.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 294375 0.31% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 798153 0.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 93469913 # Number of insts commited each cycle -system.cpu.commit.count 51987478 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 93510390 # Number of insts commited each cycle +system.cpu.commit.count 52001215 # Number of instructions committed system.cpu.commit.fp_insts 6017 # Number of committed floating point instructions. -system.cpu.commit.function_calls 529811 # Number of function calls committed. -system.cpu.commit.int_insts 42411675 # Number of committed integer instructions. -system.cpu.commit.loads 9176268 # Number of loads committed +system.cpu.commit.function_calls 530196 # Number of function calls committed. +system.cpu.commit.int_insts 42424846 # Number of committed integer instructions. +system.cpu.commit.loads 9179779 # Number of loads committed system.cpu.commit.membars 3 # Number of memory barriers committed -system.cpu.commit.refs 16251703 # Number of memory references committed +system.cpu.commit.refs 16257314 # Number of memory references committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 51864248 # Number of Instructions Simulated -system.cpu.committedInsts_total 51864248 # Number of Instructions Simulated -system.cpu.cpi 3.186866 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.186866 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses::0 111590 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 111590 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14996.059342 # average LoadLockedReq miss latency +system.cpu.committedInsts 51877985 # Number of Instructions Simulated +system.cpu.committedInsts_total 51877985 # Number of Instructions Simulated +system.cpu.cpi 3.186812 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.186812 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses::0 111585 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 111585 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14975.470534 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11857.982282 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 105119 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 105119 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 97039500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.057989 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 6471 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 6471 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 940 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 65586500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.049565 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11849.665522 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 105103 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 105103 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 97071000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.058090 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 6482 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 6482 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 951 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 65540500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.049568 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_misses 5531 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 9392794 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9392794 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 14764.348504 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses::0 9397671 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9397671 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 14774.624992 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13258.945954 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13259.657075 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 8903858 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 8903858 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 7218821500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.052054 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 488936 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 488936 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 240332 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3296227000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.026468 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 8908615 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 8908615 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 7225619000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.052040 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 489056 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 489056 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 240430 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3296695500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.026456 # mshr miss rate for ReadReq accesses _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
