It's been a while, but this is what I remember augmented by some Googling. It's xAPIC which is the second version of the APIC architecture. The first version was just called APIC, and the third and current version is called x2APIC. There was a fairly detailed section of the Intel manuals about it which is what I based my implementation on. AMD added some information about it in their manuals a while ago, and back then it wasn't quite as complete. That may be different now.
Gabe On 06/23/11 21:26, Nilay Vaish wrote: > May I know where can I find the documentation for APIC, using which > the gem5 version has been implemented? > > Thanks > Nilay > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
