On Mon, 27 Jun 2011, Gabe Black wrote:
On 06/24/11 08:38, Nilay Vaish wrote:
On Sun, 26 Jun 2011, Gabe Black wrote:
It's been a while, but this is what I remember augmented by some
Googling. It's xAPIC which is the second version of the APIC
architecture. The first version was just called APIC, and the third and
current version is called x2APIC. There was a fairly detailed section of
the Intel manuals about it which is what I based my implementation on.
AMD added some information about it in their manuals a while ago, and
back then it wasn't quite as complete. That may be different now.
Gabe
On 06/23/11 21:26, Nilay Vaish wrote:
May I know where can I find the documentation for APIC, using which
the gem5 version has been implemented?
Thanks
Nilay
Thanks Gabe.
In x86/interrupts.cc, several variables are serialized one after
another. Is there some documentation on what these variables are?
Thanks
Nilay
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Hey, sorry for the delay getting back to you. No, there is no
documentation for it right now, although you could probably understand
most of it by looking at the manual and the source. Roughly, and with no
guarantee of accuracy, this is what I think they're for.
regs -> array of architecturally visible register values
clock -> current "time"? "time" for the timer to go off? clock period?
pending*, *Vector -> if an interrupt of a particular type is waiting,
and what its vector is
startedUp -> whether or not the APIC is in the special mode where it
will respond to a startup IPI, which (if I remember correctly) are only
valid after an init IPI
pendingUnmaskableInt -> Whether one of the super interrupts (my term)
are waiting
pendingIPIs -> whether any IPIs are pending, I think?
IRRV-> the IRR (interrupt request register)
ISRV -> the ISR (in service register)
timer event stuff
Gabe
Gabe, thanks for the help!
--
Nilay
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