Thanks for your answer but my general field is software. If possible please explain your answer.
Best Regards On Fri, Jul 15, 2011 at 11:16 PM, Nilay <[email protected]> wrote: > On Thu, July 14, 2011 6:56 am, Hamid Reza Khaleghzadeh wrote: > > Hi > > > > I arrived conclusion that data is being sent to the cache which incurred > > the > > write miss form Patterson book, page 233. when a write miss occurs, > > coherency message makes "request data and make P (requester) the > exclusive > > owner". could you tell me what the meaning of request data is? > > > > > > On Thu, Jul 14, 2011 at 11:34 AM, Nilay <[email protected]> wrote: > > > >> On Thu, July 14, 2011 1:40 am, Hamid Reza Khaleghzadeh wrote: > >> > By the way, I have a question about MOESI-directory protocol. Could > >> you > >> > tell > >> > me when a write miss occurs for an address and this address exists in > >> > another cache, why this data read to requested cache and then write > >> > operation is done? > >> > > >> How did you arrive at the conclusion that the data is being sent to the > >> cache which incurred the write miss? > >> > > It could be because the coherence permissions can be fetched > speculatively. In case the speculation fails, the data still needs to be > around. > > -- > Nilay > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Hamid Reza Khaleghzadeh
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