On Mon, 25 Jul 2011, Carole-Jean Wu wrote:
Hi,
I am trying to load the ruby cache memory module for my Linux X86 simulated
system. However, simulation won't start because certain memory bus/dma
controller is not implemented in the current release. Is this true? Or am I
missing something?
If you are using TimingSimple CPU, then I expect gem5 to work for X86 +
Ruby combination.
--
Nilay
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