Unfortunately, it seems that since you asked for a patch and no one responded, then no one has the patch for what you're looking for. You'll have to dig into the code and add those stats yourself. Similar for the bug-fixing you describe later.
If you do get into that, then m5-dev can help you debug as long as you provide details of what you are doing along the way (command lines, what you tried, what you theorize the problem to be, etc.) On Fri, Jul 29, 2011 at 4:15 AM, Paolo Grani <[email protected]> wrote: > No one.... > > Paolo > > > Il 26/07/2011 11:58, Paolo Grani ha scritto: > > Hi all, >> >> i need some clarification about the ruby statistics. >> I read in a previous post that the miss counts for the ruby cache only >> works with the MOESI_hammer coherence protocol. >> I would like to know if there is some patch to get the >> MOESI_CMP_directory protocol working with this information. >> In fact when a try to run a simulation whit this protocol i get this >> output for any CacheMemory in Ruby: >> >> "Cache Stats: system.l1_cntrl0.**L1DcacheMemory >> system.l1_cntrl0.**L1DcacheMemory_total_misses: 0 >> system.l1_cntrl0.**L1DcacheMemory_total_demand_**misses: 0 >> system.l1_cntrl0.**L1DcacheMemory_total_**prefetches: 0 >> system.l1_cntrl0.**L1DcacheMemory_total_sw_**prefetches: 0 >> system.l1_cntrl0.**L1DcacheMemory_total_hw_**prefetches: 0" >> >> >> In addition i'm also interested in latency informations on memory >> accesses. >> Running a simulation always with MOESI_CMP_directory i get this: >> >> "miss_latency: [binsize: 8 max: 825 count: 19954053 average: 3.10522 | >> standard deviation: 3.91114 | 19923362 3729 6244 6396 3738 1081 119 79 >> 121 88 87 31 31 27 34 30 36 31 35 371 2435 2496 957 663 874 529 110 29 >> 27 19 21 17 13 19 16 12 15 16 11 7 9 4 5 5 7 3 9 7 1 5 2 3 0 4 2 3 3 0 1 >> 1 1 1 3 1 1 1 0 1 0 0 0 1 2 0 1 0 2 1 2 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 >> 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 >> 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 >> 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]" >> >> >> For what i can understand this information says "how many requests took >> 1 cycle, 2 cycles, 3 cycles... to be accomplished" also reporting some >> aggregate information (count,average....). >> But the the coherence protocol models a 2-level cache architecture so i >> would like to know if this informations are for the L2 shared cache or >> for the L1 level. >> If the answer is L1 level this information is an aggregate of all the >> private L1 caches (i'm running a 8 cores simulation so there are 8 >> private L1 caches) or is specific for some L1 cache? >> >> >> Finally i found a patch that tries to convert the Ruby's stats to the >> M5-style Stat class. >> I can correctly compile the code but when i try to run it a memory leak >> occurs. >> Someboy have tried to fix it? >> >> >> Thank's in advance, >> >> Paolo >> >> > > -- > ==============================**====================== > The devil is in the details > ==============================**====================== > > Ing. Paolo Grani > Dipartimento di Ingegneria dell'Informazione > via Roma 56, 53100 Siena, Italia > Laboratorio di Architettura dei Calcolatori ---> int. 223 > > mailto:[email protected] > http://www.dii.unisi.it > ==============================**====================== > ______________________________**_________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/**mailman/listinfo/gem5-users<http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users> > -- - Korey
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
