Hello Gem-5 users! I am trying to determine the miss penalties for the various cache levels of my system (ALPHA_FS). I am simulating a simple 2 level cache, where the L1 has a hit latency of '1ns' and the L2 has a hit latency of '5ns'. I have set memory to a hit latency of '80ns'. I have a calculation I am trying to do that requires the penalty for an L1 miss that hits in L2, and the penalty for an L2 miss that hits in memory. Though it would see that determining these values requires knowledge of how exactly the Classic cache memory hierarchy handles cache misses. The code concerning timing on Cache accesses is convoluted at best, and it would seem that these miss penalties could be easily calculated from the above numbers if a conceptual understanding of the behavior of the cache hierarchy is available. I havent been able to find anything on how the Classic cache hierarchy handles misses on the online documentation.
Two questions: 1) What would the miss penalty be for an access that misses in L1, but hits in L2? A simplistic model of this miss penalty would be the hit latency of L2 plus the hit latency of L1 (since the block would need to be brought to L1), but this does not account for transfer time between cache levels. 2) What would the miss penalty be for an access that misses in L2 but hits in memory? The same concerns for point 1 apply here as well. Does anyone have any more information on how exactly a cache miss is serviced in the Classic memory model? Or know where I can find said information? Thanks as always, Alex
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