In my experiment, we don't need to consider TLB. I want to disable the statistics information about TLB.
On Sun, Sep 18, 2011 at 8:05 PM, Steve Reinhardt <[email protected]> wrote: > Ha, I see now that I misinterpreted your original response... when you said > "not built in" I thought you were referring to the TLB and not to a > mechanism to disable the TLB. Sorry about that. > > Getting back to the original question, what we really need to know is what > you're trying to do, i.e., why do you think you need to disable the TLB? > There may be solutions to your actual problem that don't involve disabling > the TLB. > > Steve > > > On Sun, Sep 18, 2011 at 4:31 PM, Gabe Black <[email protected]> wrote: > >> ** >> There is a physical address space, a virtual address space, a generalized >> mechanism for mapping between the two, and the architecture's TLB is used to >> cache translations (except in MIPS, apparently). The problem is that if you >> were to have identity mapping, the simulator would put, say, the stack in a >> region that may not have any memory under it. The same goes for the other >> part of the binary image. You would have to make the compiler put the >> segments of the ELF in regions of the virtual address space that would >> identity map to appropriate regions of the physical address space, and also >> make gem5 put dynamic areas like the stack, mmap region, and heap in those >> regions. It's all possible, but not out of the box or with normal binaries. >> >> Gabe >> >> >> On 09/18/11 16:07, Steve Reinhardt wrote: >> >> If ARM is like other ISAs, doesn't it still support a physical address >> space in SE mode just to map sparse virtual addresses to a contiguous >> zero-based address range, and still use a TLB to cache translations? >> >> Steve >> >> On Sat, Sep 17, 2011 at 4:58 PM, Gabriel Michael Black < >> [email protected]> wrote: >> >>> Not built in. ARM_SE is intended to run user space programs, and those >>> aren't set up to run from the physical address space. >>> >>> Gabe >>> >>> >>> Quoting xxx <[email protected]>: >>> >>> Hello, >>>> I want to disable the TLB in ARM_SE. >>>> Is it possible? If so, how can I disable it? >>>> >>>> >>>> Thanks, >>>> Joshua >>>> >>>> >>> >>> >>> _______________________________________________ >>> gem5-users mailing list >>> [email protected] >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>> >> >> >> _______________________________________________ >> gem5-users mailing >> [email protected]http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> >> >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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