hi i tried to implement the hierarchy in the attached file using different logics but have always managed to do it wrong
I need this kind of hierarchy, if any one has already coded this kind of hierarchy, it will be great if you can send me your code or share your idea's . The following are the ways I tried to implement it. Idea 1 For every two processors and i am creating the L2cache for two processor then i am connecting that L2 to L3bus . Idea 2i I am giving the processor id like 00 for one processor and 01 for second processor Then i am connecting the two processors if the first bit in the processor id is 0 and also the first bit in the second processor is 0 and i am creating the L2 with id of 0...and in same way of next two processor also . if any one has coded these kind of hierarchy pls do send it to me ....
cache .ppt.odg
Description: application/vnd.oasis.opendocument.graphics
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
