In Ruby, directory controller = memory controller. It's a bit of a misnomer unfortunately.
On Wed, Oct 12, 2011 at 2:46 PM, LI Zhongqi <[email protected]>wrote: > Hi, > > We are trying to model a multiple memory controllers system. When I > look inside the interconnect, I found > > http://gem5.org/File:Interconnection_network.jpg > > which implies there should be memory controllers connecting to the > interconnect. > > However, from Mesh.py, I only find the L1 and L2 Cache Controllers, > DMA Controllers and Directory Controllers connecting to the > interconnect. I didn't see any memory controller is explicitly > connected to the interconnect. We are using MOESI_Directory_CMP > protocol. > > Any clue that how I could implement multiple memory controllers? > > Basically I think my question is: as long as there is no explicit > memory controller in the interconnect, which component actually > supplies the off-chip memory data? Is it the directory controller? > Thank you! > > -- > Best regards, > > ================= > Zhongqi Li > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- - Korey
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